317
Compact Models for Ultrathin Body FETs
Thus, if the fin is sufficiently thin with a thickness, t fin , smaller than L, then
SCEs are suppressed and subthreshold slope (S) is expected to be near its
ideal value of about 60 mV per decade (at room temperature) [29]. Thus, the
new device architecture results in a new scaling rule given in Equation 9.3;
that is, L can be scaled by maintaining the condition t fin < L, relaxing the scaling of gate dielectric and body doping.
In 1988 and 1999, 45 and 18 nm working DG-FinFETs, respectively, were
reported [30,31]. Subsequently, 10 nm double-gate [32], 10 nm triple-gate
(Q gate) [33], 5 nm nanowire [34], and 3 nm all-around gate [35] FinFETs
were reported.
9.2.2 UTB-SOI Device Structure
Figure 9.4 shows 3D cross section of an ideal UTB-SOI transistor structure.
If t fin in an SOI-MOSFET is only several nanometers (e.g., thinner than about
one-half of L), the leakage paths far from the gate will be eliminated and
SCEs can be significantly suppressed. It is found that the transistor leakage
current is reduced by about ten times for every nanometer drop in t fin [37].
The UTB-SOI MOSFETs require SOI substrates with extremely uniform silicon films (sub-nanometer uniformity). In 2009, SOI wafer supplier, Soitec,
developed SOI wafers with a desired tolerance of ±0.5 nm using a process
called smart cut [51]. It is reported that UTB-SOI MOSFETs with t fin ≈ 3 nm
have been experimentally realized [52]. The most attractive channel materials for UTB-SOI MOSFETs are the monolayer semiconductors such as graphene [22], MoS 2 [23], and WSe 2 monolayer [53].
Raised source
Bulk-like
isolation
Raised drain
Gate
Bo x
S p a c e r
Gate
oxide
Ultrathin body
Su bs tra te (w ell )
Body bias
FIGURE 9.4
3D cross section of an ultrathin body SOI MOSFET device structure: the body can be a thin
film of silicon, or any monolayer semiconductors; appropriate thickness of the buried oxide,
BOx can be used as the back gate oxide to bias the body for the target dynamic V th shift. (Data
from N. Paydavosi et al., IEEE Access, 1, pp. 201–215, 2013.)
Compact Models for Ultrathin Body FETs
Thus, if the fin is sufficiently thin with a thickness, t fin , smaller than L, then
SCEs are suppressed and subthreshold slope (S) is expected to be near its
ideal value of about 60 mV per decade (at room temperature) [29]. Thus, the
new device architecture results in a new scaling rule given in Equation 9.3;
that is, L can be scaled by maintaining the condition t fin < L, relaxing the scaling of gate dielectric and body doping.
In 1988 and 1999, 45 and 18 nm working DG-FinFETs, respectively, were
reported [30,31]. Subsequently, 10 nm double-gate [32], 10 nm triple-gate
(Q gate) [33], 5 nm nanowire [34], and 3 nm all-around gate [35] FinFETs
were reported.
9.2.2 UTB-SOI Device Structure
Figure 9.4 shows 3D cross section of an ideal UTB-SOI transistor structure.
If t fin in an SOI-MOSFET is only several nanometers (e.g., thinner than about
one-half of L), the leakage paths far from the gate will be eliminated and
SCEs can be significantly suppressed. It is found that the transistor leakage
current is reduced by about ten times for every nanometer drop in t fin [37].
The UTB-SOI MOSFETs require SOI substrates with extremely uniform silicon films (sub-nanometer uniformity). In 2009, SOI wafer supplier, Soitec,
developed SOI wafers with a desired tolerance of ±0.5 nm using a process
called smart cut [51]. It is reported that UTB-SOI MOSFETs with t fin ≈ 3 nm
have been experimentally realized [52]. The most attractive channel materials for UTB-SOI MOSFETs are the monolayer semiconductors such as graphene [22], MoS 2 [23], and WSe 2 monolayer [53].
Raised source
Bulk-like
isolation
Raised drain
Gate
Bo x
S p a c e r
Gate
oxide
Ultrathin body
Su bs tra te (w ell )
Body bias
FIGURE 9.4
3D cross section of an ultrathin body SOI MOSFET device structure: the body can be a thin
film of silicon, or any monolayer semiconductors; appropriate thickness of the buried oxide,
BOx can be used as the back gate oxide to bias the body for the target dynamic V th shift. (Data
from N. Paydavosi et al., IEEE Access, 1, pp. 201–215, 2013.)