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Compact Models for Integrated Circuit Design
In order to overcome the increasing challenges in continuous scaling of the
conventional planar MOSFETs, the major research and development efforts
for the last two decades have been exploring alternative device architectures
and materials [20–28]. Among the exploratory devices, FinFETs [29–36] and
UTB-SOI MOSFETs [37–40] have emerged as the most promising devices for
advanced nanometer scale VLSI (very-large-scale-integrated) technology
and beyond. The multiple-gates of multigate FETs offer strong electrostatic
control over the channel and reduce the coupling between the source and
drain in the subthreshold region, thus enabling continuous scaling of FETs.
Multigate FETs have a great potential to mitigate the risk of process variability by using undoped channel. The efforts are under way to enable largescale manufacturing of multigate FETs [41–44]. A reduction of four orders
of magnitude in the leakage current over the 32 nm planar manufacturing
process has been reported [29]. UTB-SOI FETs [45], deeply depleted channel MOSFETs [46], and BH-halo MOSFETs [47] are close competitors to the
FinFET architecture along with IBM’s aggressively scaled planar MOSFET
down to the 10 nm node [48]. Thus, ultrathin body enables continuous scaling down of FETs by overcoming the major scaling constraints such as SCE
and random discrete doping (RDD) of the conventional bulk MOSFETs discussed in Chapters 5 and 8. For computer analysis of the performance of
these emerging multigate FETs in VLSI circuits, compact models are critical.
This chapter presents surface potential–based compact models for multigate
FET devices.
9.2 Multigate Device Structures
The desirables from any alternative device structure include surmounting
the impending L scaling barrier, preserving today’s CMOS technology as
much as possible, and using innovative device architectures to eliminate
major problems in scaled planar MOSFETs including undesirable leakage
currents and excessive static power. Among the alternative architectures,
FinFETs [29–36] and UTB-MOSFETs [37–40] are found to offer solutions to
major issues for the continuous scaling of FETs. Both of these structures
show potential to eliminate the leakage paths that are far from the gate(s) by
limiting the thickness of semiconductor body in the immediate vicinity of
the gate(s) [29].
9.2.1 Bulk-Multigate Device Structure
Figure 9.1 shows a 3D cross section of an ideal double-gate MOSFET
(DG-MOSFET) device structure [49]. As shown in Figure 9.1, the structure
consists of a thin film of undoped silicon body, referred to as the fin, a front
Compact Models for Integrated Circuit Design
In order to overcome the increasing challenges in continuous scaling of the
conventional planar MOSFETs, the major research and development efforts
for the last two decades have been exploring alternative device architectures
and materials [20–28]. Among the exploratory devices, FinFETs [29–36] and
UTB-SOI MOSFETs [37–40] have emerged as the most promising devices for
advanced nanometer scale VLSI (very-large-scale-integrated) technology
and beyond. The multiple-gates of multigate FETs offer strong electrostatic
control over the channel and reduce the coupling between the source and
drain in the subthreshold region, thus enabling continuous scaling of FETs.
Multigate FETs have a great potential to mitigate the risk of process variability by using undoped channel. The efforts are under way to enable largescale manufacturing of multigate FETs [41–44]. A reduction of four orders
of magnitude in the leakage current over the 32 nm planar manufacturing
process has been reported [29]. UTB-SOI FETs [45], deeply depleted channel MOSFETs [46], and BH-halo MOSFETs [47] are close competitors to the
FinFET architecture along with IBM’s aggressively scaled planar MOSFET
down to the 10 nm node [48]. Thus, ultrathin body enables continuous scaling down of FETs by overcoming the major scaling constraints such as SCE
and random discrete doping (RDD) of the conventional bulk MOSFETs discussed in Chapters 5 and 8. For computer analysis of the performance of
these emerging multigate FETs in VLSI circuits, compact models are critical.
This chapter presents surface potential–based compact models for multigate
FET devices.
9.2 Multigate Device Structures
The desirables from any alternative device structure include surmounting
the impending L scaling barrier, preserving today’s CMOS technology as
much as possible, and using innovative device architectures to eliminate
major problems in scaled planar MOSFETs including undesirable leakage
currents and excessive static power. Among the alternative architectures,
FinFETs [29–36] and UTB-MOSFETs [37–40] are found to offer solutions to
major issues for the continuous scaling of FETs. Both of these structures
show potential to eliminate the leakage paths that are far from the gate(s) by
limiting the thickness of semiconductor body in the immediate vicinity of
the gate(s) [29].
9.2.1 Bulk-Multigate Device Structure
Figure 9.1 shows a 3D cross section of an ideal double-gate MOSFET
(DG-MOSFET) device structure [49]. As shown in Figure 9.1, the structure
consists of a thin film of undoped silicon body, referred to as the fin, a front