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9
Compact Models for Ultrathin Body FETs
9.1 Introduction
This chapter presents compact models for the emerging ultrathin-body
(UTB) field-effect-transistors (FETs). The UTB FETs include multiple-gate or
multigate FinFETs and silicon-on-insulator (SOI) multigate UTB-FETs (UTBSOI FETs) [1,2]. FinFETs and UTB-SOI FETs have emerged as the real alternatives to MOSFETs (metal-oxide-semiconductor field-effect transistors) and
planar CMOS (complementary metal-oxide-semiconductor) technology to
surmount the continuous scaling challenges of MOSFET devices. The continuous miniaturization of the conventional planar MOSFET devices has
become more challenging at the same rate of Moore’s law [3–6] due to several fundamental device-physics constraints such as short channel effects
(SCEs). Shrinking the gate length, L, in the decananometer regime degrades
the transfer characteristics of planar MOSFETs, degrades the subthreshold
swing (S), and decreases V th (e.g., V th roll-off) [3] as discussed in Chapter 5. This
implies that the scaled MOSFETs cannot be turned off easily by lowering the
gate voltage V g due to SCEs [7]. Because of SCEs, the device characteristics become increasingly sensitive to L variations and process-induced variability imposes a serious challenge in continued scaling of bulk MOSFETs as
discussed in Chapter 8 [8,9]. The early theoretical and modeling approaches on
SCEs [10–12] suggest increasing the gate control by reducing the gate dielectric thickness in proportion to L, which increases manufacturing process complexity. Another constraint for the continuous scaling of conventional bulk
MOSFETs is controlling leakage current in scaled devices [12]. It is observed
that at gate length below 20 nm, the leakage paths several nanometers below
the silicon-dielectric interface (subsurface leakage paths) are primarily responsible for the leakage current. These leakage paths are weakly controlled by
the gate irrespective of gate oxide thickness and their potential barriers can be
easily lowered by drain bias V d through the enhanced electric field coupling
to the drain, referred to as the drain-induced barrier lowering [12]. This new
challenge to scaling L led to engineering efforts on channel-profile engineering,
shallow source-drain extensions (SDE), and halo implants around SDEs as discussed in Chapter 5 [13–19].
9
Compact Models for Ultrathin Body FETs
9.1 Introduction
This chapter presents compact models for the emerging ultrathin-body
(UTB) field-effect-transistors (FETs). The UTB FETs include multiple-gate or
multigate FinFETs and silicon-on-insulator (SOI) multigate UTB-FETs (UTBSOI FETs) [1,2]. FinFETs and UTB-SOI FETs have emerged as the real alternatives to MOSFETs (metal-oxide-semiconductor field-effect transistors) and
planar CMOS (complementary metal-oxide-semiconductor) technology to
surmount the continuous scaling challenges of MOSFET devices. The continuous miniaturization of the conventional planar MOSFET devices has
become more challenging at the same rate of Moore’s law [3–6] due to several fundamental device-physics constraints such as short channel effects
(SCEs). Shrinking the gate length, L, in the decananometer regime degrades
the transfer characteristics of planar MOSFETs, degrades the subthreshold
swing (S), and decreases V th (e.g., V th roll-off) [3] as discussed in Chapter 5. This
implies that the scaled MOSFETs cannot be turned off easily by lowering the
gate voltage V g due to SCEs [7]. Because of SCEs, the device characteristics become increasingly sensitive to L variations and process-induced variability imposes a serious challenge in continued scaling of bulk MOSFETs as
discussed in Chapter 8 [8,9]. The early theoretical and modeling approaches on
SCEs [10–12] suggest increasing the gate control by reducing the gate dielectric thickness in proportion to L, which increases manufacturing process complexity. Another constraint for the continuous scaling of conventional bulk
MOSFETs is controlling leakage current in scaled devices [12]. It is observed
that at gate length below 20 nm, the leakage paths several nanometers below
the silicon-dielectric interface (subsurface leakage paths) are primarily responsible for the leakage current. These leakage paths are weakly controlled by
the gate irrespective of gate oxide thickness and their potential barriers can be
easily lowered by drain bias V d through the enhanced electric field coupling
to the drain, referred to as the drain-induced barrier lowering [12]. This new
challenge to scaling L led to engineering efforts on channel-profile engineering,
shallow source-drain extensions (SDE), and halo implants around SDEs as discussed in Chapter 5 [13–19].