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Compact Models for Integrated Circuit Design
c. Repeat part (b) for W = 30 nm to calculate and plot σV th,RDD as a
function of L on the same graph (b).
d. Compare your results in parts (b) and (c) and explain.
e. Repeat parts (b) and (c) for C = 0.7071; explain the difference, if any.
8.3 Use the given technology parameters in exercise 8.2 to solve the following problems (consider only RDD):
a. Estimate mismatch coefficient A vt for the nMOSFET devices of
the technology using C = 0.8165.
b. Use the estimated A vt number from part (a) to calculate σ(ΔV th )
for a set of devices with varying W and L and plot σ(ΔV th ) versus
1/ W L
⋅ . Explain your plot.
c. Repeat part (a) to calculate σV th for a set of devices with varying
W and L and plot σV th versus 1/ W L
⋅ . Explain your results.
d. Compare results from part (b) and part (c) and explain the significance of each plot in compact MOSFET modeling.
First of all, select a wide W (~2 μm) and keeping W constant vary L
from the nominal geometry to a long (~250 nm) device and calculate
the area W.L; then select a long L (=200 nm) and keeping L constant
vary W from the nominal geometry to a wide device (~1 μm) and
calculate W.L.
8.4 If the distance between the identical paired transistors in the x direction is D x , write an expression for the variance σ ∆P
2 of the stochastic
parameter P showing the correction factor due to separation between
the transistors of the pair.
8.5 Following references [23,24] derive Equation 8.2. Clearly state any
assumptions you make.