311
Modeling Process Variability in Scaled MOSFETs
8.7 Summary
This chapter presented the intrinsic process variability in CMOS technology
and different approaches to model process variability in VLSI circuit CAD.
A brief overview of the systematic and stochastic front-end process variability
and sources of process variability is described. A methodology to characterize the random process variability that causes mismatch in the performance
of identical MOSFETs in a die is discussed. Conventional approaches to generate compact MOSFET variability models are overviewed and a detailed statistical MOSFET compact modeling approach is discussed. The basic steps to
generate statistical compact MOSFET models including selection of expressions defining device performance, selection of device parameters sensitive
to process variability, mapping process-variability sensitive device parameters to corresponding compact model parameters, and model formulation
are described. The results obtained by MC statistical model and statistical
corner model are presented. The basic statistical modeling methodology can
be used to generate statistical compact MOSFET models using any compact
models considering the basic equations for device performance. Finally, different approaches to mitigate the risk of process variability in VLSI circuits
are briefly discussed.
Exercises
8.1 Write an expression for variance σ β
β
∆
2
2
(
) for mismatch in current
factor β (a) in terms of the variance of its mutually independent components described in Section 8.5.1.1 and (b) in terms of the mismatch
coefficient of each component.
8.2 Consider an nMOSFET device with channel length L = 100 nm, channel width W = 200 nm, channel doping concentration N a = 5 × 10 17 cm −3 ,
T ox = 1 nm, and S/D junction depth X j = 50 nm of the 100 nm CMOS
technology node; use C = 0.8165 to solve the following problems:
a. Scale down the above technology by 70% up to five times and
calculate the total number of dopants (N total ) in the channel for all
the technology nodes and plot N total versus L. (Scaling: multiply
all geometry parameters by 0.7 and divide doping by 0.7.)
b. Considering the device with W = 200 nm, calculate and plot
σV th,RDD as a function of L calculated in part (a); assume L = L eff
and W = W eff .
Modeling Process Variability in Scaled MOSFETs
8.7 Summary
This chapter presented the intrinsic process variability in CMOS technology
and different approaches to model process variability in VLSI circuit CAD.
A brief overview of the systematic and stochastic front-end process variability
and sources of process variability is described. A methodology to characterize the random process variability that causes mismatch in the performance
of identical MOSFETs in a die is discussed. Conventional approaches to generate compact MOSFET variability models are overviewed and a detailed statistical MOSFET compact modeling approach is discussed. The basic steps to
generate statistical compact MOSFET models including selection of expressions defining device performance, selection of device parameters sensitive
to process variability, mapping process-variability sensitive device parameters to corresponding compact model parameters, and model formulation
are described. The results obtained by MC statistical model and statistical
corner model are presented. The basic statistical modeling methodology can
be used to generate statistical compact MOSFET models using any compact
models considering the basic equations for device performance. Finally, different approaches to mitigate the risk of process variability in VLSI circuits
are briefly discussed.
Exercises
8.1 Write an expression for variance σ β
β
∆
2
2
(
) for mismatch in current
factor β (a) in terms of the variance of its mutually independent components described in Section 8.5.1.1 and (b) in terms of the mismatch
coefficient of each component.
8.2 Consider an nMOSFET device with channel length L = 100 nm, channel width W = 200 nm, channel doping concentration N a = 5 × 10 17 cm −3 ,
T ox = 1 nm, and S/D junction depth X j = 50 nm of the 100 nm CMOS
technology node; use C = 0.8165 to solve the following problems:
a. Scale down the above technology by 70% up to five times and
calculate the total number of dopants (N total ) in the channel for all
the technology nodes and plot N total versus L. (Scaling: multiply
all geometry parameters by 0.7 and divide doping by 0.7.)
b. Considering the device with W = 200 nm, calculate and plot
σV th,RDD as a function of L calculated in part (a); assume L = L eff
and W = W eff .