309
Modeling Process Variability in Scaled MOSFETs
8.6 Mitigation of the Risk of Process Variability
in VLSI Circuit Performance
Techniques to mitigate the risk of process variability include (1) pure process optimization such as targeting key transistor properties to reduce
RDD, improve patterning techniques to reduce LER, and improve polishing techniques to reduce systematic cross-wafer variation; (2) combination of process and design techniques such as optimization of topology,
use of OPC to reduce random and systematic variations, and adding
dummy features to reduce systematic variations; and (3) pure design
techniques such as common-centroid layout to compensate for systematic
variation.
As we discussed in Section 8.2.2.1, RDD is a major contributor to random variation and is modeled by Equation 8.2. From Equation 8.2, it is
found that we can reduce the impact of RDD by reducing channel doping, N, and gate oxide thickness, T ox . In advanced CMOS technologies, T ox
is scaled appropriately using Hi-K dielectric with metal gate to mitigate
the risk of process variability due to OTV. However, due to the scaling
constraint of N CH , RDD cannot be controlled in nanoscale planar CMOS
technology.
Recently, advanced channel engineering has been used to design
nanoscale MOSFET devices with undoped or lightly doped channel to
mitigate the risk of RDD [48]. The channel is formed on undoped epitaxial layer grown on silicon substrate followed by standard CMOS processing steps [58]. Also, it has been shown that the double-halo MOSFET
device architecture [5–8] controls the V th variation in nanoscale devices.
Recently, an enhanced double-halo MOSFET [7] device architecture is
proposed to design undoped or lightly doped channel MOSFETs and
mitigate the risk of process variability in planar CMOS technology [59].
This enhanced double-halo structure is referred to as the buried-halo
MOSFET (BH-MOSFET), which is shown in Figure 8.10. The simulation
results shown in Figure 8.11 show a significant reduction of threshold
voltage variation due to RDD in nanoscale BH-MOSFETs compared to the
conventional MOSFET devices.
In order to further mitigate the risk of process variability in nonplanar
devices and technologies including Fin field-effect transistors (FinFETs) and
ultrathin body (UTB) silicon-on-insulator field-effect transistors referred to
as the UTB-SOI MOSFETs [60] have emerged as the most promising alternatives to MOSFET devices and CMOS technology. An overview of the compact models for these devices is presented in Chapter 9.
Modeling Process Variability in Scaled MOSFETs
8.6 Mitigation of the Risk of Process Variability
in VLSI Circuit Performance
Techniques to mitigate the risk of process variability include (1) pure process optimization such as targeting key transistor properties to reduce
RDD, improve patterning techniques to reduce LER, and improve polishing techniques to reduce systematic cross-wafer variation; (2) combination of process and design techniques such as optimization of topology,
use of OPC to reduce random and systematic variations, and adding
dummy features to reduce systematic variations; and (3) pure design
techniques such as common-centroid layout to compensate for systematic
variation.
As we discussed in Section 8.2.2.1, RDD is a major contributor to random variation and is modeled by Equation 8.2. From Equation 8.2, it is
found that we can reduce the impact of RDD by reducing channel doping, N, and gate oxide thickness, T ox . In advanced CMOS technologies, T ox
is scaled appropriately using Hi-K dielectric with metal gate to mitigate
the risk of process variability due to OTV. However, due to the scaling
constraint of N CH , RDD cannot be controlled in nanoscale planar CMOS
technology.
Recently, advanced channel engineering has been used to design
nanoscale MOSFET devices with undoped or lightly doped channel to
mitigate the risk of RDD [48]. The channel is formed on undoped epitaxial layer grown on silicon substrate followed by standard CMOS processing steps [58]. Also, it has been shown that the double-halo MOSFET
device architecture [5–8] controls the V th variation in nanoscale devices.
Recently, an enhanced double-halo MOSFET [7] device architecture is
proposed to design undoped or lightly doped channel MOSFETs and
mitigate the risk of process variability in planar CMOS technology [59].
This enhanced double-halo structure is referred to as the buried-halo
MOSFET (BH-MOSFET), which is shown in Figure 8.10. The simulation
results shown in Figure 8.11 show a significant reduction of threshold
voltage variation due to RDD in nanoscale BH-MOSFETs compared to the
conventional MOSFET devices.
In order to further mitigate the risk of process variability in nonplanar
devices and technologies including Fin field-effect transistors (FinFETs) and
ultrathin body (UTB) silicon-on-insulator field-effect transistors referred to
as the UTB-SOI MOSFETs [60] have emerged as the most promising alternatives to MOSFET devices and CMOS technology. An overview of the compact models for these devices is presented in Chapter 9.