291
Modeling Process Variability in Scaled MOSFETs
variation. This I g variation induces a voltage drop in the polysilicon gate
and significantly changes V th . In addition, the device transconductance g m
changes significantly because of the reduction in the gate voltage V gs due to
the voltage drop in the polysilicon gate. In high-k gate dielectric and metal
gate devices, OTV introduces significant mobility degradation [1,9].
8.2.2.4 Other Sources Process Variability
Other sources of process variability include variation associated with polysilicon as well as metal gates granularity [30,31]; variation in fixed charge
[32] and defects and traps in gate dielectric [33]; variation associated with
patterning proximity effects such as optical proximity correction [34];
variation associated with polish such as shallow trench isolation [35] and
gate [36]; variation associated with the strain such as in wafer-level biaxial
strain [37], high-stress capping layers [38], and embedded silicon germanium (SiGe) [39]; and variation associated with implants and anneals due to
implant tools, the implant profile, and millisecond annealing [40,41].
Thus, from the above discussions, it is clear that the advanced CMOS
process technologies introduce within-die random performance variability, which causes severe variability in the performance of advanced VLSI
circuits and systems. Therefore, it is critical to accurately model process
variability when predicting the performance of advanced VLSI circuits and
systems.
8.3 Characterization of Parametric Variability in MOSFETs
The random parametric variation such as threshold voltage variation (σV th )
is a key factor in determining the yield of memory elements such as SRAM
and register file cells. Equation 8.3 can be used to characterize random V th
variation in devices.
8.3.1 Random Variability
In Figure 8.1, the random variability of a parameter is defined as the variation around its mean value. Therefore, random variability can be characterized by monitoring the differences in the value of a parameter of two closely
spaced identical transistors, that is, paired transistor. Thus, the random V th
variation of identical transistor pairs can be determined by measuring the
difference in V th (i.e., ΔV th ) between a number of sets of closely spaced paired
transistors (e.g., all the transistor pairs on a wafer) and computing the standard deviation of the difference ΔV th (i.e., σΔV th ). Thus
Modeling Process Variability in Scaled MOSFETs
variation. This I g variation induces a voltage drop in the polysilicon gate
and significantly changes V th . In addition, the device transconductance g m
changes significantly because of the reduction in the gate voltage V gs due to
the voltage drop in the polysilicon gate. In high-k gate dielectric and metal
gate devices, OTV introduces significant mobility degradation [1,9].
8.2.2.4 Other Sources Process Variability
Other sources of process variability include variation associated with polysilicon as well as metal gates granularity [30,31]; variation in fixed charge
[32] and defects and traps in gate dielectric [33]; variation associated with
patterning proximity effects such as optical proximity correction [34];
variation associated with polish such as shallow trench isolation [35] and
gate [36]; variation associated with the strain such as in wafer-level biaxial
strain [37], high-stress capping layers [38], and embedded silicon germanium (SiGe) [39]; and variation associated with implants and anneals due to
implant tools, the implant profile, and millisecond annealing [40,41].
Thus, from the above discussions, it is clear that the advanced CMOS
process technologies introduce within-die random performance variability, which causes severe variability in the performance of advanced VLSI
circuits and systems. Therefore, it is critical to accurately model process
variability when predicting the performance of advanced VLSI circuits and
systems.
8.3 Characterization of Parametric Variability in MOSFETs
The random parametric variation such as threshold voltage variation (σV th )
is a key factor in determining the yield of memory elements such as SRAM
and register file cells. Equation 8.3 can be used to characterize random V th
variation in devices.
8.3.1 Random Variability
In Figure 8.1, the random variability of a parameter is defined as the variation around its mean value. Therefore, random variability can be characterized by monitoring the differences in the value of a parameter of two closely
spaced identical transistors, that is, paired transistor. Thus, the random V th
variation of identical transistor pairs can be determined by measuring the
difference in V th (i.e., ΔV th ) between a number of sets of closely spaced paired
transistors (e.g., all the transistor pairs on a wafer) and computing the standard deviation of the difference ΔV th (i.e., σΔV th ). Thus