290
Compact Models for Integrated Circuit Design
σV
C
W L
th RDD
vt
eff eff
,
=
(8.3)
where C vt is a process technology dependent constant given by
C
C
q
N
T
vt
si B CH
ox
ox
≅ ⋅ (
)
3
4
ε φ
ε
(8.4)
Equation 8.3 shows that V th variability due to RDD is inversely proportional
to the square root of device area. Thus, Equation 8.3 can be used to model
the impact of RDD-induced V th variability and the parameter C vt is the slope
of σV th,RDD versus 1/ W L
eff eff plots obtained from a large set of measurement
data on a set of paired devices with varying W and L.
8.2.2.2 Line-Edge Roughness
In CMOS technology, LER results from sub-wavelength lithography and
etching processes that cause variation in the critical dimension of the
transistor feature size, as shown in Figure 8.2 [26]. The impact of LER
includes variation in V th and higher subthreshold current. LER-induced
V th mismatch depends on the variability in W eff of MOSFETs and is given
by [1,9,26,27]
σ
σ
V
W
V
th LER
eff
th RDD
,
,
∝
<
1
(8.5)
Thus, LER increases as VLSI technology scales down. In scaled MOSFET
devices, LER has become a larger fraction of L and a major source of intrinsic
statistical variation, causing significant variability in VLSI device and circuit
performance. The mismatch due to LER and RDD is statistically independent and can be modeled independently [1,9,26].
8.2.2.3 Oxide Thickness Variation
In CMOS technologies, OTV, shown in Figure 8.2, is caused by atomic
level interface roughness between silicon and gate dielectric and remote
interface roughness between gate material and gate dielectric, hereafter
referred to as the surface roughness (SR). This SR causes fluctuations of the
voltage drop across the oxide layer, resulting in V th variation [1,9,28,29]. In
nanoscale MOSFETs, OTV is becoming more dominant as T ox approaches
the length of a few silicon atoms and is comparable to the thickness of
interface roughness.
In nano-MOSFET devices, OTV causes significant device parameter variability. In polysilicon gate MOSFETs, OTV introduces a gate current (I g )
Compact Models for Integrated Circuit Design
σV
C
W L
th RDD
vt
eff eff
,
=
(8.3)
where C vt is a process technology dependent constant given by
C
C
q
N
T
vt
si B CH
ox
ox
≅ ⋅ (
)
3
4
ε φ
ε
(8.4)
Equation 8.3 shows that V th variability due to RDD is inversely proportional
to the square root of device area. Thus, Equation 8.3 can be used to model
the impact of RDD-induced V th variability and the parameter C vt is the slope
of σV th,RDD versus 1/ W L
eff eff plots obtained from a large set of measurement
data on a set of paired devices with varying W and L.
8.2.2.2 Line-Edge Roughness
In CMOS technology, LER results from sub-wavelength lithography and
etching processes that cause variation in the critical dimension of the
transistor feature size, as shown in Figure 8.2 [26]. The impact of LER
includes variation in V th and higher subthreshold current. LER-induced
V th mismatch depends on the variability in W eff of MOSFETs and is given
by [1,9,26,27]
σ
σ
V
W
V
th LER
eff
th RDD
,
,
∝
<
1
(8.5)
Thus, LER increases as VLSI technology scales down. In scaled MOSFET
devices, LER has become a larger fraction of L and a major source of intrinsic
statistical variation, causing significant variability in VLSI device and circuit
performance. The mismatch due to LER and RDD is statistically independent and can be modeled independently [1,9,26].
8.2.2.3 Oxide Thickness Variation
In CMOS technologies, OTV, shown in Figure 8.2, is caused by atomic
level interface roughness between silicon and gate dielectric and remote
interface roughness between gate material and gate dielectric, hereafter
referred to as the surface roughness (SR). This SR causes fluctuations of the
voltage drop across the oxide layer, resulting in V th variation [1,9,28,29]. In
nanoscale MOSFETs, OTV is becoming more dominant as T ox approaches
the length of a few silicon atoms and is comparable to the thickness of
interface roughness.
In nano-MOSFET devices, OTV causes significant device parameter variability. In polysilicon gate MOSFETs, OTV introduces a gate current (I g )