287
Modeling Process Variability in Scaled MOSFETs
current specifications. In the semiconductor industry, the systematic process
variation has been the major interest to IC chip manufacturers in maintaining competitive yield over multiple technology nodes [4]. The systematic process variability in manufacturing technology has been accounted in compact
modeling by defining process corners, that is, boundaries in parameter variation that account for process tolerances [1,9].
8.2.2 Random or Local Process Variability
The random variation in IC device and chip performance arises from stochastic variations inherent to the discrete nature of dopant impurities and
point defects as well as random variations in the complex processing steps
of nanometer scale CMOS technology. Random variability is defined as the
local or intra-die process variability [1,9]. Local process variability causes
parametric fluctuations or mismatch between identically designed devices
within a die as shown in Figure 8.1. The major sources of intrinsic process
variability in advanced CMOS technologies include random discrete doping
(RDD), line-edge roughness (LER), line-width roughness (LWR), and oxide
thickness variation (OTV) as shown in Figure 8.2 [1,9–13].
The front-end process variability in CMOS technology has been extensively studied and the major sources of process variability along with their
impact on device and VLSI circuit performance have been reported [1,9–11].
In the following section, a brief overview of the sources of front-end process
variability is presented.
8.2.2.1 Random Discrete Doping
In the channel region of a MOSFET device, RDD results from the discreteness
of dopant atoms as shown in Figure 8.2. In a MOSFET device, the channel
RDD
Substrate
Gate
W
X j
V = W * L * X j
LWR
L
S o u r c e
D
r a i n
O
T V
L E R
FIGURE 8.2
The critical sources of variability in CMOS devices; here L, W, and X j are the channel length,
channel width, and S/D junction depth of MOSFET devices, respectively; and V is the volume
of charge in the channel region. (Data from S.K. Saha, IEEE Access, 2, 104–115, 2014.)
Modeling Process Variability in Scaled MOSFETs
current specifications. In the semiconductor industry, the systematic process
variation has been the major interest to IC chip manufacturers in maintaining competitive yield over multiple technology nodes [4]. The systematic process variability in manufacturing technology has been accounted in compact
modeling by defining process corners, that is, boundaries in parameter variation that account for process tolerances [1,9].
8.2.2 Random or Local Process Variability
The random variation in IC device and chip performance arises from stochastic variations inherent to the discrete nature of dopant impurities and
point defects as well as random variations in the complex processing steps
of nanometer scale CMOS technology. Random variability is defined as the
local or intra-die process variability [1,9]. Local process variability causes
parametric fluctuations or mismatch between identically designed devices
within a die as shown in Figure 8.1. The major sources of intrinsic process
variability in advanced CMOS technologies include random discrete doping
(RDD), line-edge roughness (LER), line-width roughness (LWR), and oxide
thickness variation (OTV) as shown in Figure 8.2 [1,9–13].
The front-end process variability in CMOS technology has been extensively studied and the major sources of process variability along with their
impact on device and VLSI circuit performance have been reported [1,9–11].
In the following section, a brief overview of the sources of front-end process
variability is presented.
8.2.2.1 Random Discrete Doping
In the channel region of a MOSFET device, RDD results from the discreteness
of dopant atoms as shown in Figure 8.2. In a MOSFET device, the channel
RDD
Substrate
Gate
W
X j
V = W * L * X j
LWR
L
S o u r c e
D
r a i n
O
T V
L E R
FIGURE 8.2
The critical sources of variability in CMOS devices; here L, W, and X j are the channel length,
channel width, and S/D junction depth of MOSFET devices, respectively; and V is the volume
of charge in the channel region. (Data from S.K. Saha, IEEE Access, 2, 104–115, 2014.)