285
8
Modeling Process Variability
in Scaled MOSFETs
8.1 Introduction
This chapter presents compact MOSFET (metal-oxide-semiconductor fieldeffect transistor) modeling approaches for process variability-aware VLSI
(very-large-scale-integrated) circuit CAD. The circuit design for advanced
VLSI technology is severely constrained by random and systematic process variability [1]. With continued miniaturization of MOSFET devices
[2–8], performance variability induced by process variability has become a
critical issue in the design of VLSI circuits using advanced CMOS (complementary metal-oxide-semiconductor) technologies. Process variability in
scaled CMOS technologies severely impacts the delay and power variability in VLSI devices, circuits, and chips, and this impact keeps increasing as
MOSFET devices and CMOS technologies continue to scale down [1,9–13].
The increasing amount of within-die process variability on the yield of VLSI
circuits, such as static random access memory (SRAM), has imposed an enormous challenge in the conventional VLSI design methodologies. Similarly,
the chip mean variation due to across-the-chip systematic process variability also imposes serious challenge in the conventional VLSI circuit design
methodologies. Because of process variability constraints, an advanced VLSI
circuit, optimized using the conventional design methodology, is more susceptible to random performance fluctuations. Thus, new circuit design techniques to account for the impact of process variability in VLSI circuits have
become essential [1,9]. And, compact model addressing the impact of random
and systematic process variability in scaled MOSFET devices is crucial for
the simulation and analysis of advanced VLSI circuits. Process variability in
manufacturing technology includes front-end or intrinsic process variability
due to various dopant implant and thermal processing steps and back-end
variability of metal lines for interconnecting the devices in the VLSI circuits.
Both the front-end and interconnection process variabilities are important
for circuit analysis. Over the years, different approaches have been used to
develop statistical models for circuit analysis to account for intrinsic process
8
Modeling Process Variability
in Scaled MOSFETs
8.1 Introduction
This chapter presents compact MOSFET (metal-oxide-semiconductor fieldeffect transistor) modeling approaches for process variability-aware VLSI
(very-large-scale-integrated) circuit CAD. The circuit design for advanced
VLSI technology is severely constrained by random and systematic process variability [1]. With continued miniaturization of MOSFET devices
[2–8], performance variability induced by process variability has become a
critical issue in the design of VLSI circuits using advanced CMOS (complementary metal-oxide-semiconductor) technologies. Process variability in
scaled CMOS technologies severely impacts the delay and power variability in VLSI devices, circuits, and chips, and this impact keeps increasing as
MOSFET devices and CMOS technologies continue to scale down [1,9–13].
The increasing amount of within-die process variability on the yield of VLSI
circuits, such as static random access memory (SRAM), has imposed an enormous challenge in the conventional VLSI design methodologies. Similarly,
the chip mean variation due to across-the-chip systematic process variability also imposes serious challenge in the conventional VLSI circuit design
methodologies. Because of process variability constraints, an advanced VLSI
circuit, optimized using the conventional design methodology, is more susceptible to random performance fluctuations. Thus, new circuit design techniques to account for the impact of process variability in VLSI circuits have
become essential [1,9]. And, compact model addressing the impact of random
and systematic process variability in scaled MOSFET devices is crucial for
the simulation and analysis of advanced VLSI circuits. Process variability in
manufacturing technology includes front-end or intrinsic process variability
due to various dopant implant and thermal processing steps and back-end
variability of metal lines for interconnecting the devices in the VLSI circuits.
Both the front-end and interconnection process variabilities are important
for circuit analysis. Over the years, different approaches have been used to
develop statistical models for circuit analysis to account for intrinsic process