3
Introduction to Compact Models
model. For MOSFET devices, device phenomena accompanying the core
model include short-channel effects (SCEs), output conductance, quantum
mechanical effects (QMEs), nonuniform doping effects, gate leakage current,
band-to-band tunneling, noise, non-quasistatic (NQS) effect, intrinsic input
resistance, and strain effect [4,6].
The compact model for circuit CAD is the bridge between the circuit design
and processing groups and is a module of the extended technology CAD
(TCAD) environment [7]. In the extended TCAD environment, the compact
model plays an important role in developing next generation IC fabrication
technology and assesses the manufacturability of IC fabrication processes by
reverse modeling [7,8].
1.1.2 Compact Interconnect Models
Today’s very-large-scale-integrated (VLSI) circuits consist of MOSFET devices
and their interconnections, referred to as interconnects. In a typical VLSI chip,
the active area is about 10% whereas the physical area is occupied by interconnect and isolation regions 6–10 times the active device area [9]. For this
reason, the role of the interconnect is becoming increasingly important as the
feature size is scaled down to decananometer regimes and the device density
is increased on the chip. As VLSI technology shrinks below 22-nm geometries with Cu/low-k interconnections, parasitics due to interconnections are
becoming a limiting factor in determining circuit performance. Therefore,
accurate modeling of interconnect parasitic resistance (R), capacitance (C),
and inductance (L) is essential in determining various on-chip interconnectrelated issues, such as delay, cross talk, energy losses in R due to the current
(I) flow or IR drop, and power dissipation. Accurate compact interconnect
models are crucial for the design and optimization of advanced VLSI circuits
for 22-nm CMOS technology and beyond. In addition, with the emergence
of technologies such as carbon nanotubes and graphene nanoribbons,
compact interconnection models that are suitable for these technologies
are crucial for advanced circuit design. Currently available interconnect
models, which are based on field solvers, are inadequate for accurate and
meaningful analyses of today’s chips, which house millions of devices.
Interconnect models can accurately simulate on-chip global interconnections and speed-power optimization for advanced interconnect technologies. Modeling of these interconnect properties is thus important and
must be included by the designer when checking circuit performance in
circuit CAD. Though interconnect models are an essential part of optimizing VLSI circuit performance, interconnect modeling is outside the
scope of this book; interested readers may refer Saha et al. [10] for recent
development of interconnect models. In this treatise, compact modeling of
field-effect transistors (FETs) and their parasitic components that are used
in the mainstream VLSI circuit design are described.
Introduction to Compact Models
model. For MOSFET devices, device phenomena accompanying the core
model include short-channel effects (SCEs), output conductance, quantum
mechanical effects (QMEs), nonuniform doping effects, gate leakage current,
band-to-band tunneling, noise, non-quasistatic (NQS) effect, intrinsic input
resistance, and strain effect [4,6].
The compact model for circuit CAD is the bridge between the circuit design
and processing groups and is a module of the extended technology CAD
(TCAD) environment [7]. In the extended TCAD environment, the compact
model plays an important role in developing next generation IC fabrication
technology and assesses the manufacturability of IC fabrication processes by
reverse modeling [7,8].
1.1.2 Compact Interconnect Models
Today’s very-large-scale-integrated (VLSI) circuits consist of MOSFET devices
and their interconnections, referred to as interconnects. In a typical VLSI chip,
the active area is about 10% whereas the physical area is occupied by interconnect and isolation regions 6–10 times the active device area [9]. For this
reason, the role of the interconnect is becoming increasingly important as the
feature size is scaled down to decananometer regimes and the device density
is increased on the chip. As VLSI technology shrinks below 22-nm geometries with Cu/low-k interconnections, parasitics due to interconnections are
becoming a limiting factor in determining circuit performance. Therefore,
accurate modeling of interconnect parasitic resistance (R), capacitance (C),
and inductance (L) is essential in determining various on-chip interconnectrelated issues, such as delay, cross talk, energy losses in R due to the current
(I) flow or IR drop, and power dissipation. Accurate compact interconnect
models are crucial for the design and optimization of advanced VLSI circuits
for 22-nm CMOS technology and beyond. In addition, with the emergence
of technologies such as carbon nanotubes and graphene nanoribbons,
compact interconnection models that are suitable for these technologies
are crucial for advanced circuit design. Currently available interconnect
models, which are based on field solvers, are inadequate for accurate and
meaningful analyses of today’s chips, which house millions of devices.
Interconnect models can accurately simulate on-chip global interconnections and speed-power optimization for advanced interconnect technologies. Modeling of these interconnect properties is thus important and
must be included by the designer when checking circuit performance in
circuit CAD. Though interconnect models are an essential part of optimizing VLSI circuit performance, interconnect modeling is outside the
scope of this book; interested readers may refer Saha et al. [10] for recent
development of interconnect models. In this treatise, compact modeling of
field-effect transistors (FETs) and their parasitic components that are used
in the mainstream VLSI circuit design are described.