217
Compact Models for Small Geometry MOSFETs
where
Y
I
I V V
X V V
m
lB
sub
ds
ds
dsat
ds
dsat
i i
=
−
=
−
= −
(
)
(
)
1
(5.128)
and
c
A
B
i
i
=
ln
Equation 5.127 represents a straight line with the slope, m, and intercept, c,
given by Equation 5.128. Thus, ln I I V V
sub
ds
d s
d sat
−
(
)
versus 1 V V
ds
dsat
−
(
)
plot is a straight line with a slope m = – l i B i and the intercept c = ln(A i /B i ).
From such plots for MOSFETs with different processing parameters, the
value of l i can be determined [47] as shown in Figure 5.20.
As discussed in Section 5.3.6, substrate current I sub flowing into the substrate
increases drain current significantly, resulting in lower output resistance as
shown in Figure 5.13. This is due to the fact that I sub flowing to the substrate
causes an IR drop in the substrate, resulting in a body bias; this body bias forward biases the source/body pn-junction thus lowering the source to chain
potential barrier for carriers. As a result, more carriers are injected from the
source to the inversion channel, causing a significant increase in I ds , which is
referred to as the SCBE. The SCBE causes V th drop and manifold increase in
I sub and consequently, I dS as shown in Figure 5.13
0.2
10 −10
10 −9
10 −8
10 −7
10 −6
10 −5
10 −4
10 −3
10 −2
L eff = 0.64 μm
L eff = 0.48 μm
V GS = 1.0 V
V GS = 1.5 V
V GS = 2.0 V
V GS = 1.0 V
V GS = 1.5 V
V GS = 2.0 V
0.4
0.6
X (1/V)
Y (1/V)
0.8
1.0
FIGURE 5.20
Plot of Y I
I V V
sub
d s
d s
d sat
=
−
(
)
/
versus X V V
ds
dsat
=
−
(
)
−1 with different V gs for LDD type nMOSFETs of different channel length; all data are obtained under V bs = 0 for W = 40 μm devices and
T ox = 150 A. (Data from S. Saha, Solid-State Electron., 37, 1786–1788, 1994.)
Compact Models for Small Geometry MOSFETs
where
Y
I
I V V
X V V
m
lB
sub
ds
ds
dsat
ds
dsat
i i
=
−
=
−
= −
(
)
(
)
1
(5.128)
and
c
A
B
i
i
=
ln
Equation 5.127 represents a straight line with the slope, m, and intercept, c,
given by Equation 5.128. Thus, ln I I V V
sub
ds
d s
d sat
−
(
)
versus 1 V V
ds
dsat
−
(
)
plot is a straight line with a slope m = – l i B i and the intercept c = ln(A i /B i ).
From such plots for MOSFETs with different processing parameters, the
value of l i can be determined [47] as shown in Figure 5.20.
As discussed in Section 5.3.6, substrate current I sub flowing into the substrate
increases drain current significantly, resulting in lower output resistance as
shown in Figure 5.13. This is due to the fact that I sub flowing to the substrate
causes an IR drop in the substrate, resulting in a body bias; this body bias forward biases the source/body pn-junction thus lowering the source to chain
potential barrier for carriers. As a result, more carriers are injected from the
source to the inversion channel, causing a significant increase in I ds , which is
referred to as the SCBE. The SCBE causes V th drop and manifold increase in
I sub and consequently, I dS as shown in Figure 5.13
0.2
10 −10
10 −9
10 −8
10 −7
10 −6
10 −5
10 −4
10 −3
10 −2
L eff = 0.64 μm
L eff = 0.48 μm
V GS = 1.0 V
V GS = 1.5 V
V GS = 2.0 V
V GS = 1.0 V
V GS = 1.5 V
V GS = 2.0 V
0.4
0.6
X (1/V)
Y (1/V)
0.8
1.0
FIGURE 5.20
Plot of Y I
I V V
sub
d s
d s
d sat
=
−
(
)
/
versus X V V
ds
dsat
=
−
(
)
−1 with different V gs for LDD type nMOSFETs of different channel length; all data are obtained under V bs = 0 for W = 40 μm devices and
T ox = 150 A. (Data from S. Saha, Solid-State Electron., 37, 1786–1788, 1994.)