184
Compact Models for Integrated Circuit Design
as channel length decreases. The physics of SCE can be understood by a
simple mathematical model based on charge sharing [32,33]. However, this
model is not suitable for circuit CAD. Therefore, compact models are developed to calculate the shift in V th due to SCE for circuit CAD.
Again, for a particular V gs > V th , as the drain voltage increases, the depletion region near the drain end of the channel gradually increases and extends
toward the source end of the channel. As a result, the potential barrier to the
inversion charge near the source end is reduced so that more carriers are
injected from the source to the channel as V ds increases. Thus, for a particular value of V gs more inversion charges are injected as L decreases. This is
referred to as the DIBL, causing V th fall with the increase in V ds as shown in
Figure 5.6.
In order to model SCE, we solve Poisson’s equation in the y direction along
the channel. It can be shown that the shift in V th due to SCE and DIBL is given
by [34]
∆V
L
V
V
th
th
eff
b i
s
ds
SCE DIBL
,
(
)= − ( )
−
(
)+
θ
φ
2
(5.20)
where
θ th eff
eff
t
L
L
l
( )=
(
) −
1
2
2
1
cosh
(5.21)
V bi is the built-in potential of the S/D pn-junctions and is given by
(Equation 2.84)
V v
N N
n
bi
kT
CH SD
i
=
ln
2
(5.22)
p-Substrate
Q b depleted
by source
Q b depleted
by drain
Depletion
region
Oxide
n+ Source
n+ Drain
Gate
V s
V d
X d
FIGURE 5.5
Short channel effect in MOSFETs caused by bulk-charge sharing by the gate and S/D pnjunctions; a significant part of channel depletion is caused by S/D regions; the source and
drain each contributes an amount of channel charge Q b to the total channel charge in silicon;
X d is the width of the S/D depletion region at zero bias condition.
Compact Models for Integrated Circuit Design
as channel length decreases. The physics of SCE can be understood by a
simple mathematical model based on charge sharing [32,33]. However, this
model is not suitable for circuit CAD. Therefore, compact models are developed to calculate the shift in V th due to SCE for circuit CAD.
Again, for a particular V gs > V th , as the drain voltage increases, the depletion region near the drain end of the channel gradually increases and extends
toward the source end of the channel. As a result, the potential barrier to the
inversion charge near the source end is reduced so that more carriers are
injected from the source to the channel as V ds increases. Thus, for a particular value of V gs more inversion charges are injected as L decreases. This is
referred to as the DIBL, causing V th fall with the increase in V ds as shown in
Figure 5.6.
In order to model SCE, we solve Poisson’s equation in the y direction along
the channel. It can be shown that the shift in V th due to SCE and DIBL is given
by [34]
∆V
L
V
V
th
th
eff
b i
s
ds
SCE DIBL
,
(
)= − ( )
−
(
)+
θ
φ
2
(5.20)
where
θ th eff
eff
t
L
L
l
( )=
(
) −
1
2
2
1
cosh
(5.21)
V bi is the built-in potential of the S/D pn-junctions and is given by
(Equation 2.84)
V v
N N
n
bi
kT
CH SD
i
=
ln
2
(5.22)
p-Substrate
Q b depleted
by source
Q b depleted
by drain
Depletion
region
Oxide
n+ Source
n+ Drain
Gate
V s
V d
X d
FIGURE 5.5
Short channel effect in MOSFETs caused by bulk-charge sharing by the gate and S/D pnjunctions; a significant part of channel depletion is caused by S/D regions; the source and
drain each contributes an amount of channel charge Q b to the total channel charge in silicon;
X d is the width of the S/D depletion region at zero bias condition.