175
5
Compact Models for Small Geometry MOSFETs
5.1 Introduction
In this chapter the compact models for small geometry MOSFET (metal-oxidesemiconductor field-effect transistors) devices are presented. The continuous
scaling of MOSFET devices toward decananometer regime has resulted in
higher device density and faster circuit speed along with higher power dissipation [1–4]. Many new physical phenomena became significant with the
device dimension rapidly approaching its physical limit. These include small
geometry effects [5–8], channel length modulation (CLM) [9], drain-induced
barrier lowering (DIBL) [10], velocity saturation [11], mobility degradation due
to high vertical electric field [12], impact ionization [13], band-to-band tunneling [14], velocity overshoot [15], self-heating [16], inversion-layer quantization
[17–19], polysilicon depletion [20], and process variability [21,22]. Thus, accurate
MOSFET models that include the observed new physical phenomena are crucial to design and optimization of advanced very-large-scale-integrated (VLSI)
circuits using nanoscale complementary metal-oxide-semiconductor (CMOS)
technologies. In this chapter, we will use regional modeling approach to
develop compact MOSFET models to accurately simulate different physical and
small geometry effects in advanced VLSI circuits. First of all, we will derive different analytical expressions to model the deviation of long channel V th model
derived in Chapter 4 due to geometry and different physical effects and present
an accurate V th model for circuit CAD. Then we derive drain current model for
short channel MOSFET devices considering high-field effects causing mobility
degradation and velocity saturation.
5.2 Threshold Voltage Model
MOSFET threshold voltage model developed in Chapter 4 assumes uniformly doped substrate and neglects geometry effects on device performance. The expression for V th for long channel MOSFETs with uniformly
doped substrate is given by Equation 4.12 and can be generalized as
5
Compact Models for Small Geometry MOSFETs
5.1 Introduction
In this chapter the compact models for small geometry MOSFET (metal-oxidesemiconductor field-effect transistors) devices are presented. The continuous
scaling of MOSFET devices toward decananometer regime has resulted in
higher device density and faster circuit speed along with higher power dissipation [1–4]. Many new physical phenomena became significant with the
device dimension rapidly approaching its physical limit. These include small
geometry effects [5–8], channel length modulation (CLM) [9], drain-induced
barrier lowering (DIBL) [10], velocity saturation [11], mobility degradation due
to high vertical electric field [12], impact ionization [13], band-to-band tunneling [14], velocity overshoot [15], self-heating [16], inversion-layer quantization
[17–19], polysilicon depletion [20], and process variability [21,22]. Thus, accurate
MOSFET models that include the observed new physical phenomena are crucial to design and optimization of advanced very-large-scale-integrated (VLSI)
circuits using nanoscale complementary metal-oxide-semiconductor (CMOS)
technologies. In this chapter, we will use regional modeling approach to
develop compact MOSFET models to accurately simulate different physical and
small geometry effects in advanced VLSI circuits. First of all, we will derive different analytical expressions to model the deviation of long channel V th model
derived in Chapter 4 due to geometry and different physical effects and present
an accurate V th model for circuit CAD. Then we derive drain current model for
short channel MOSFET devices considering high-field effects causing mobility
degradation and velocity saturation.
5.2 Threshold Voltage Model
MOSFET threshold voltage model developed in Chapter 4 assumes uniformly doped substrate and neglects geometry effects on device performance. The expression for V th for long channel MOSFETs with uniformly
doped substrate is given by Equation 4.12 and can be generalized as