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Compact Models for Integrated Circuit Design
advanced industry standard models for circuit computer-aided design
(CAD). Our objective is to determine the drain current for any combination of DC voltages. First of all, we will present a brief overview of the basic
MOSFET structure as used in VLSI technology, its features and behavior
under operating biases, and the basic theory of MOSFET device operation and characteristics. One of the most important physical parameters of
MOSFET device operation is the threshold voltage, V th , defined as the gate
voltage at which the device starts to turn on. In this chapter, we will develop
the basic theory of V th modeling for long channel devices. Throughout this
chapter we will assume that the channel is sufficiently long and wide, so that
the edge effects are negligibly small. Unless stated otherwise, we will also
assume that the substrate is uniformly doped p-type silicon. We will introduce the relevant basic drain current models in a systematic way, deriving
them from an important model and relating them to the source and to each
other. Before, describing large geometry model, we first present a brief overview of MOSFET device architecture for better appreciation of MOSFET
compact models.
4.2 Overview of MOSFET Devices
An ideal MOSFET device structure is shown in Figure 4.1 and a 2D (twodimensional) cross section is shown in Figure 4.2. The structure includes a
semiconductor substrate such as silicon on which a thin insulating layer such
as SiO 2 of thickness T ox is grown. A conducting layer (a metal or degenerately
doped polycrystalline silicon) called gate electrode is deposited on the top
of the gate oxide. Two heavily doped regions of depth X j , called the source
and drain, are formed in the substrate on either side of the gate. The source
and drain regions overlap with the gate at its two ends. The source-to-drain
regions are equivalent to two back-to-back pn-junctions. This region between
the source and drain near the silicon surface is called the channel region. Thus,
in essence, a MOSFET is essentially an MOS capacitor with two back-to-bask
pn-junctions at the two ends of the gate. In advanced VLSI circuits, NMOS
(p-type body with n+ source-drain) and PMOS (n-type body with p+ sourcedrain) are fabricated together using shallow trench isolation (STI) and is called
the CMOS transistor. Thus, the STI shown in Figure 4.2 is used to isolate various devices fabricated on the same substrate. For device operation, a MOSFET
is a four-terminal device with gate g, source s, drain d, and substrate or body b.
The device is symmetrical and cannot be distinguished without the applied
bias. The body terminal allows to modulating the inversion layer from the
gate as well as body to offer more flexibility of devices at circuit operation.
As shown in Figure 4.1, a MOSFET device is characterized by channel
length L, channel width W, gate oxide with thickness T ox , substrate doping N b ,
and source-drain with junction depth X j . In advanced VLSI circuits, NMOS
(p-type body with n+ source-drain) and PMOS (n-type body with p+ sourcedrain) are used together and is called the complementary MOS transistor.
Compact Models for Integrated Circuit Design
advanced industry standard models for circuit computer-aided design
(CAD). Our objective is to determine the drain current for any combination of DC voltages. First of all, we will present a brief overview of the basic
MOSFET structure as used in VLSI technology, its features and behavior
under operating biases, and the basic theory of MOSFET device operation and characteristics. One of the most important physical parameters of
MOSFET device operation is the threshold voltage, V th , defined as the gate
voltage at which the device starts to turn on. In this chapter, we will develop
the basic theory of V th modeling for long channel devices. Throughout this
chapter we will assume that the channel is sufficiently long and wide, so that
the edge effects are negligibly small. Unless stated otherwise, we will also
assume that the substrate is uniformly doped p-type silicon. We will introduce the relevant basic drain current models in a systematic way, deriving
them from an important model and relating them to the source and to each
other. Before, describing large geometry model, we first present a brief overview of MOSFET device architecture for better appreciation of MOSFET
compact models.
4.2 Overview of MOSFET Devices
An ideal MOSFET device structure is shown in Figure 4.1 and a 2D (twodimensional) cross section is shown in Figure 4.2. The structure includes a
semiconductor substrate such as silicon on which a thin insulating layer such
as SiO 2 of thickness T ox is grown. A conducting layer (a metal or degenerately
doped polycrystalline silicon) called gate electrode is deposited on the top
of the gate oxide. Two heavily doped regions of depth X j , called the source
and drain, are formed in the substrate on either side of the gate. The source
and drain regions overlap with the gate at its two ends. The source-to-drain
regions are equivalent to two back-to-back pn-junctions. This region between
the source and drain near the silicon surface is called the channel region. Thus,
in essence, a MOSFET is essentially an MOS capacitor with two back-to-bask
pn-junctions at the two ends of the gate. In advanced VLSI circuits, NMOS
(p-type body with n+ source-drain) and PMOS (n-type body with p+ sourcedrain) are fabricated together using shallow trench isolation (STI) and is called
the CMOS transistor. Thus, the STI shown in Figure 4.2 is used to isolate various devices fabricated on the same substrate. For device operation, a MOSFET
is a four-terminal device with gate g, source s, drain d, and substrate or body b.
The device is symmetrical and cannot be distinguished without the applied
bias. The body terminal allows to modulating the inversion layer from the
gate as well as body to offer more flexibility of devices at circuit operation.
As shown in Figure 4.1, a MOSFET device is characterized by channel
length L, channel width W, gate oxide with thickness T ox , substrate doping N b ,
and source-drain with junction depth X j . In advanced VLSI circuits, NMOS
(p-type body with n+ source-drain) and PMOS (n-type body with p+ sourcedrain) are used together and is called the complementary MOS transistor.