131
4
Large Geometry MOSFET Compact Models
4.1 Introduction
In the two-terminal MOS (metal-oxide-semiconductor) capacitor system in
Chapter 3, we have discussed that an inversion condition can be reached
by a certain applied gate bias to form a thin layer of minority carrier concentration (e.g., electron) in the majority carrier (e.g., p-type) silicon surface
at the silicon/SiO 2 interface. Under this inversion condition, the thermally
generated minority carriers diffuse to the surface to form the inversion
layer in the majority carrier substrate. However, it is difficult to sustain this
minority carrier inversion layer in a majority carrier substrate from thermal
generation and subsequent diffusion of these carriers to the surface without a steady source of carrier supply. Therefore, a heavily doped minority
carrier region (e.g., n+ region in a p-type substrate), called the source (s), is
added to the MOS structure as a terminal for the steady supply of minority carriers at the inversion condition. And, a complete MOSFET (metaloxide- semiconductor field-effect transistor) structure is formed by adding
one more terminal, called the drain (d), with a heavily doped region with
the doping-type same as the source region. These source and drain terminals contact the two opposite ends of the inversion layer so that a potential
difference can be applied across this layer and cause a current flow in the
MOSFET structure. In this chapter, we will develop the basic mathematical
models of this current flow from the source to drain of MOSFET devices,
referred to as the drain current model.
Since the conception of MOSFETs in 1920s [1], there has been a continuous research and development effort on MOSFET device, technology, and
modeling [2–5]. As stated in Chapter 1, the basic theory of MOSFETs has
been developed in 1960s. In 1970s, complementary MOS (CMOS) technology
with MOSFET devices became the pervasive technology of mainstream VLSI
(very-large-scale-integrated) circuits. In the last five decades, there has been
a relentless pursuit of developing MOSFET compact models that accurately
simulate the experimental behavior of MOSFET devices in VLSI circuits.
In this chapter, we will present the basic MOSFET drain current models
for large geometry devices to lay the foundation for the understanding of
4
Large Geometry MOSFET Compact Models
4.1 Introduction
In the two-terminal MOS (metal-oxide-semiconductor) capacitor system in
Chapter 3, we have discussed that an inversion condition can be reached
by a certain applied gate bias to form a thin layer of minority carrier concentration (e.g., electron) in the majority carrier (e.g., p-type) silicon surface
at the silicon/SiO 2 interface. Under this inversion condition, the thermally
generated minority carriers diffuse to the surface to form the inversion
layer in the majority carrier substrate. However, it is difficult to sustain this
minority carrier inversion layer in a majority carrier substrate from thermal
generation and subsequent diffusion of these carriers to the surface without a steady source of carrier supply. Therefore, a heavily doped minority
carrier region (e.g., n+ region in a p-type substrate), called the source (s), is
added to the MOS structure as a terminal for the steady supply of minority carriers at the inversion condition. And, a complete MOSFET (metaloxide- semiconductor field-effect transistor) structure is formed by adding
one more terminal, called the drain (d), with a heavily doped region with
the doping-type same as the source region. These source and drain terminals contact the two opposite ends of the inversion layer so that a potential
difference can be applied across this layer and cause a current flow in the
MOSFET structure. In this chapter, we will develop the basic mathematical
models of this current flow from the source to drain of MOSFET devices,
referred to as the drain current model.
Since the conception of MOSFETs in 1920s [1], there has been a continuous research and development effort on MOSFET device, technology, and
modeling [2–5]. As stated in Chapter 1, the basic theory of MOSFETs has
been developed in 1960s. In 1970s, complementary MOS (CMOS) technology
with MOSFET devices became the pervasive technology of mainstream VLSI
(very-large-scale-integrated) circuits. In the last five decades, there has been
a relentless pursuit of developing MOSFET compact models that accurately
simulate the experimental behavior of MOSFET devices in VLSI circuits.
In this chapter, we will present the basic MOSFET drain current models
for large geometry devices to lay the foundation for the understanding of