121
Metal-Oxide-Semiconductor System
and not for MOS transistors. In the case of MOS transistors, the source and
drain diffusions can supply minority carriers to the inversion layer almost
instantaneously.
3.5.4 Deviation from Ideal C–V Curves
The ideal MOS capacitance plots shown in Figure 3.21 are obtained by
assuming that the gate oxide is a perfect insulator free of charges (Q 0 = 0)
and Φ ms = 0, so that V fb = 0. However, due to the nonideal nature of the MOS
structures, experimental LF and HF C–V plots deviate from the ideal behavior by one or more of the following parameters: (1) nonzero Φ ms , (2) interface traps, (3) mobile ions in the oxide, (4) fixed charge, and (5) nonuniform
substrate doping. The detailed description of the nonideal behavior of MOS
capacitor system is available in the literature [2].
3.5.5 Polysilicon Depletion Effect on C–V Curves
In our discussions so far we assumed that the polysilicon gate is degenerately doped with concentration in excess of 5 × 10 19 cm –3 . However, if the gate
is nondegenerately doped, it can no longer be treated as an equipotential
area like metal gate. In this case, the capacitance given by Equation 3.86 for a
MOS capacitor system must be modified to include the capacitance C poly due
to polysilicon depletion at the polysilicon-gate/gate-dielectric interface. For
polysilicon gate MOS capacitor, the capacitance, C, of the system is a series
combination of: (1) polysilicon depletion capacitance, C poly ; (2) oxide capacitance, C ox ; and (3) substrate capacitance, C s , as shown in Figure 3.22b. Then
the resulting gate capacitance at strong inversion is given by [14]
1
1
1
1
C C
C
C
poly
ox
s
=
+
+
(3.105)
Typical MOS C–V characteristics due to polysilicon gate depletion effect is
shown in Figure 3.23. It is observed from Figure 3.23 that as V g increases
in the inversion regime, C poly decreases due to the increase in the depletion
width, X poly-depletion of polysilicon gate causing a decrease in the total capacitance C and thereby C/C ox . Therefore, LF C–V plots show a local maximum
at a certain V g .
The C–V behavior shown in Figure 3.23 is attributed to the deviation
from the nondegenerate doping of the polysilicon gate [14–19]. The result
of the nondegenerate polysilicon doping is that the LF capacitance in inversion (C g,inv ) is much smaller than that of accumulation, and C g,inv decreases
slightly with gate bias. However, at gate bias larger than a certain voltage
C g,inv recovers to C ox rather abruptly [14–19].
The decrease in capacitance due to polysilicon depletion effect can be
expressed as an increase in the effective gate oxide thickness. The increase in
Metal-Oxide-Semiconductor System
and not for MOS transistors. In the case of MOS transistors, the source and
drain diffusions can supply minority carriers to the inversion layer almost
instantaneously.
3.5.4 Deviation from Ideal C–V Curves
The ideal MOS capacitance plots shown in Figure 3.21 are obtained by
assuming that the gate oxide is a perfect insulator free of charges (Q 0 = 0)
and Φ ms = 0, so that V fb = 0. However, due to the nonideal nature of the MOS
structures, experimental LF and HF C–V plots deviate from the ideal behavior by one or more of the following parameters: (1) nonzero Φ ms , (2) interface traps, (3) mobile ions in the oxide, (4) fixed charge, and (5) nonuniform
substrate doping. The detailed description of the nonideal behavior of MOS
capacitor system is available in the literature [2].
3.5.5 Polysilicon Depletion Effect on C–V Curves
In our discussions so far we assumed that the polysilicon gate is degenerately doped with concentration in excess of 5 × 10 19 cm –3 . However, if the gate
is nondegenerately doped, it can no longer be treated as an equipotential
area like metal gate. In this case, the capacitance given by Equation 3.86 for a
MOS capacitor system must be modified to include the capacitance C poly due
to polysilicon depletion at the polysilicon-gate/gate-dielectric interface. For
polysilicon gate MOS capacitor, the capacitance, C, of the system is a series
combination of: (1) polysilicon depletion capacitance, C poly ; (2) oxide capacitance, C ox ; and (3) substrate capacitance, C s , as shown in Figure 3.22b. Then
the resulting gate capacitance at strong inversion is given by [14]
1
1
1
1
C C
C
C
poly
ox
s
=
+
+
(3.105)
Typical MOS C–V characteristics due to polysilicon gate depletion effect is
shown in Figure 3.23. It is observed from Figure 3.23 that as V g increases
in the inversion regime, C poly decreases due to the increase in the depletion
width, X poly-depletion of polysilicon gate causing a decrease in the total capacitance C and thereby C/C ox . Therefore, LF C–V plots show a local maximum
at a certain V g .
The C–V behavior shown in Figure 3.23 is attributed to the deviation
from the nondegenerate doping of the polysilicon gate [14–19]. The result
of the nondegenerate polysilicon doping is that the LF capacitance in inversion (C g,inv ) is much smaller than that of accumulation, and C g,inv decreases
slightly with gate bias. However, at gate bias larger than a certain voltage
C g,inv recovers to C ox rather abruptly [14–19].
The decrease in capacitance due to polysilicon depletion effect can be
expressed as an increase in the effective gate oxide thickness. The increase in