Logic Gates and Related Devices
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• for a two-input AND gate, Y = AAB;
• for a three-input AND gate, Y = AABBC;
• for a four-input AND gate, Y = AABBCCD.
If we interpret the basic definition of OR and AND gates for a negative logic system, we have an
interesting observation. We find that an OR gate in a positive logic system is an AND gate in a negative
logic system. Also, a positive AND is a negative OR.
Example 4.3
Show the logic arrangement for implementing a four-input AND gate using two-input AND gates only.
Solution
Figure 4.9 shows the hardware implementation of a four-input AND gate using two-input AND gates.
The output of AND gate 1 is Y 1 = AABB The second AND gate produces an output Y 2 given by
Y 2 = Y 1C = AABBC. Similarly, the output of AND gate 3 is Y = Y 2.D = AABBCCD and hence the
result.
4.3.3 NOT Gate
A NOT gate is a one-input, one-output logic circuit whose output is always the complement of the
input. That is, a LOW input produces a HIGH output, and vice versa. When interpreted for a positive
logic system, a logic ‘0’ at the input produces a logic ‘1’ at the output, and vice versa. It is also known
as a ‘complementing circuit’ or an ‘inverting circuit’. Figure 4.10 shows the circuit symbol and the
truth table.
The NOT operation on a logic variable X is denoted as X or X
. That is, if X is the input to a NOT
circuit, then its output Y is given by Y = X or X
and reads as Y equals NOT X. Thus, if X = 0 Y = 1
and if X = 1 Y = 0.
Example 4.4
For the logic circuit arrangements of Figs 4.11(a) and (b), draw the output waveform.
Solution
In the case of the OR gate arrangement of Fig. 4.11(a), the output will be permanently in logic ‘1’
state as the two inputs can never be in logic ‘0’ state together owing to the presence of the inverter.
In the case of the AND gate arrangement of Fig. 4.11(b), the output will be permanently in logic ‘0’
state as the two inputs can never be in logic ‘1’ state together owing to the presence of the inverter.
A
B
Y1
C
D
Y2
Y=A.B.C.D
1
2
3
Figure 4.9 Implementation of a four-input AND gate using two-input AND gates.
75
• for a two-input AND gate, Y = AAB;
• for a three-input AND gate, Y = AABBC;
• for a four-input AND gate, Y = AABBCCD.
If we interpret the basic definition of OR and AND gates for a negative logic system, we have an
interesting observation. We find that an OR gate in a positive logic system is an AND gate in a negative
logic system. Also, a positive AND is a negative OR.
Example 4.3
Show the logic arrangement for implementing a four-input AND gate using two-input AND gates only.
Solution
Figure 4.9 shows the hardware implementation of a four-input AND gate using two-input AND gates.
The output of AND gate 1 is Y 1 = AABB The second AND gate produces an output Y 2 given by
Y 2 = Y 1C = AABBC. Similarly, the output of AND gate 3 is Y = Y 2.D = AABBCCD and hence the
result.
4.3.3 NOT Gate
A NOT gate is a one-input, one-output logic circuit whose output is always the complement of the
input. That is, a LOW input produces a HIGH output, and vice versa. When interpreted for a positive
logic system, a logic ‘0’ at the input produces a logic ‘1’ at the output, and vice versa. It is also known
as a ‘complementing circuit’ or an ‘inverting circuit’. Figure 4.10 shows the circuit symbol and the
truth table.
The NOT operation on a logic variable X is denoted as X or X
. That is, if X is the input to a NOT
circuit, then its output Y is given by Y = X or X
and reads as Y equals NOT X. Thus, if X = 0 Y = 1
and if X = 1 Y = 0.
Example 4.4
For the logic circuit arrangements of Figs 4.11(a) and (b), draw the output waveform.
Solution
In the case of the OR gate arrangement of Fig. 4.11(a), the output will be permanently in logic ‘1’
state as the two inputs can never be in logic ‘0’ state together owing to the presence of the inverter.
In the case of the AND gate arrangement of Fig. 4.11(b), the output will be permanently in logic ‘0’
state as the two inputs can never be in logic ‘1’ state together owing to the presence of the inverter.
A
B
Y1
C
D
Y2
Y=A.B.C.D
1
2
3
Figure 4.9 Implementation of a four-input AND gate using two-input AND gates.