Microcontrollers
575
CentralProcessingUnit
Memory
Figure 14.9 Von Neumann architecture.
Von Neumann architecture uses a single memory to hold both program instructions and data. There
is one common data and address bus between processor and memory (Fig. 14.9). Instructions and data
are fetched in sequential order, thus limiting the operation data transfer rate or the throughput. This
phenomenon is commonly referred to as the Von Neumann bottleneck. The throughput is very small
compared with the size of the memory. In present-day machines, the throughput is also very small
compared with the rate at which the processor itself can work. In the condition where the processor
is required to perform minimal processing on large amounts of data, the processor is forced to wait
for vital data to be transferred from or to memory. Microcontroller type number 68HC11 uses Von
Neumann architecture.
Harvard architecture uses physically separate memories for program instructions and data. It
therefore requires separate buses for program and data, as shown in Fig. 14.10. In such architecture,
instructions and operands can be fetched simultaneously, which makes microcontrollers using this
architecture much faster compared with the ones using Von Neumann architecture. Also, different
data and program bus widths are possible, which allows the program and data memory to be better
optimized to architectural requirements. In fact, the word width, timing, implementation technology
and memory address structure can be different in the two cases. Program memory is usually much
larger than data memory, which implies that the address bus for the program memory is wider than
the address bus for the data memory.
Central Processing Unit
Data
Memory
Program
Memory
Figure 14.10 Harvard architecture.
575
CentralProcessingUnit
Memory
Figure 14.9 Von Neumann architecture.
Von Neumann architecture uses a single memory to hold both program instructions and data. There
is one common data and address bus between processor and memory (Fig. 14.9). Instructions and data
are fetched in sequential order, thus limiting the operation data transfer rate or the throughput. This
phenomenon is commonly referred to as the Von Neumann bottleneck. The throughput is very small
compared with the size of the memory. In present-day machines, the throughput is also very small
compared with the rate at which the processor itself can work. In the condition where the processor
is required to perform minimal processing on large amounts of data, the processor is forced to wait
for vital data to be transferred from or to memory. Microcontroller type number 68HC11 uses Von
Neumann architecture.
Harvard architecture uses physically separate memories for program instructions and data. It
therefore requires separate buses for program and data, as shown in Fig. 14.10. In such architecture,
instructions and operands can be fetched simultaneously, which makes microcontrollers using this
architecture much faster compared with the ones using Von Neumann architecture. Also, different
data and program bus widths are possible, which allows the program and data memory to be better
optimized to architectural requirements. In fact, the word width, timing, implementation technology
and memory address structure can be different in the two cases. Program memory is usually much
larger than data memory, which implies that the address bus for the program memory is wider than
the address bus for the data memory.
Central Processing Unit
Data
Memory
Program
Memory
Figure 14.10 Harvard architecture.