Microprocessors
555
and an improved bus interface. The MC68030 fully supports the nonmultiplexed bus structure of the
MC68020, with 32 bits of address and 32 bits of data. The MC68030 bus has an enhanced controller
that supports both asynchronous and synchronous bus cycles and burst data transfers.
13.11.4 80486 Microprocessor
The 80486 (i486 is the trade name) offers high performance for DOS, OS/2, Windows and UNIX
System V applications. It is 100 % compatible with 80386 DX and SX microprocessors. One million
transistors integrate cache memory, floating-point hardware and a memory management unit on-chip
while retaining binary compatibility with previous members of the x86 architectural family. Frequently
used instructions execute in one cycle, resulting in RISC performance levels. An eight-byte unified
code and data cache combined with an 80/106 MB/s burst bus at 25/33 MHz ensure high system
throughput even with inexpensive DRAMs.
The 80486 microprocessor is currently available in versions operating at 25, 33, 50, 66 and 100
MHz frequency. It is available as 80486DX and 80486SX. The only difference between these two
devices is that 80486SX does not contain the numeric coprocessor. The 80487SX numeric coprocessor
is available as a separate component for the 80486SX microprocessor.
Salient features of the 80486 processor include:
1. Full binary compatibility with 386 DX CPU, 386 SX CPU, 376 embedded processor and 80286,
8086 and 8088 processors.
2. Execution unit designed to execute frequently used instructions in one clock cycle.
3. 32-bit integer processor for performing arithmetic and logical operations.
4. Internal floating-point arithmetic unit for supporting the 32-, 64- and 80-bit formats specified in
IEEE standard 754 (object-code compatible with 80387 DX and 387 SX math coprocessors).
5. Internal 8 kB cache memory, which provides fast access to recently used instructions and data.
6. Bus control signals for maintaining cache consistency in multiprocessor systems.
7. Segmentation, a form of memory management for creating independent, protected address space.
8. Paging, a form of memory management that provides access to data structures larger than the
available memory space by keeping them partly in memory and partly on disk.
9. Restartable instructions that allow a program to be restarted following an exception (necessary for
supporting demand-paged virtual memory).
10. Pipelined instruction execution overlaps the interpretation of different instructions.
11. Debugging registers for hardware support of instruction and data breakpoints.
The 80486 is object-code compatible with three other 386 processors, namely the 386 DX processor,
the 386 SX processor (16-bit data bus) and the 376 embedded processor (16-bit data bus). 80486SX is
also available in the same package with a few differences, as mentioned below:
1. Pin B15 is NMI on the 80486DX and pin A15 is NMI on 80486SX.
2. Pin A15 is IGNNE on 80486DX. It is not present on 80486SX.
3. C14 is FERR on 80486DX and pins B15 and C14 on 80486SX are not connected.
The architecture of 80486DX is almost the same as that of 80386 except that it contains a math
coprocessor and an 8K byte level 1 cache memory. 80486SX does have the math coprocessor. Figure
13.19 shows the internal architecture of 80486DX. The major difference between 80386 and 80486 is
that almost half of the instructions of 80486 execute in one clocking period instead of the two clocking
periods for the 80386 microprocessor for the same instructions.
555
and an improved bus interface. The MC68030 fully supports the nonmultiplexed bus structure of the
MC68020, with 32 bits of address and 32 bits of data. The MC68030 bus has an enhanced controller
that supports both asynchronous and synchronous bus cycles and burst data transfers.
13.11.4 80486 Microprocessor
The 80486 (i486 is the trade name) offers high performance for DOS, OS/2, Windows and UNIX
System V applications. It is 100 % compatible with 80386 DX and SX microprocessors. One million
transistors integrate cache memory, floating-point hardware and a memory management unit on-chip
while retaining binary compatibility with previous members of the x86 architectural family. Frequently
used instructions execute in one cycle, resulting in RISC performance levels. An eight-byte unified
code and data cache combined with an 80/106 MB/s burst bus at 25/33 MHz ensure high system
throughput even with inexpensive DRAMs.
The 80486 microprocessor is currently available in versions operating at 25, 33, 50, 66 and 100
MHz frequency. It is available as 80486DX and 80486SX. The only difference between these two
devices is that 80486SX does not contain the numeric coprocessor. The 80487SX numeric coprocessor
is available as a separate component for the 80486SX microprocessor.
Salient features of the 80486 processor include:
1. Full binary compatibility with 386 DX CPU, 386 SX CPU, 376 embedded processor and 80286,
8086 and 8088 processors.
2. Execution unit designed to execute frequently used instructions in one clock cycle.
3. 32-bit integer processor for performing arithmetic and logical operations.
4. Internal floating-point arithmetic unit for supporting the 32-, 64- and 80-bit formats specified in
IEEE standard 754 (object-code compatible with 80387 DX and 387 SX math coprocessors).
5. Internal 8 kB cache memory, which provides fast access to recently used instructions and data.
6. Bus control signals for maintaining cache consistency in multiprocessor systems.
7. Segmentation, a form of memory management for creating independent, protected address space.
8. Paging, a form of memory management that provides access to data structures larger than the
available memory space by keeping them partly in memory and partly on disk.
9. Restartable instructions that allow a program to be restarted following an exception (necessary for
supporting demand-paged virtual memory).
10. Pipelined instruction execution overlaps the interpretation of different instructions.
11. Debugging registers for hardware support of instruction and data breakpoints.
The 80486 is object-code compatible with three other 386 processors, namely the 386 DX processor,
the 386 SX processor (16-bit data bus) and the 376 embedded processor (16-bit data bus). 80486SX is
also available in the same package with a few differences, as mentioned below:
1. Pin B15 is NMI on the 80486DX and pin A15 is NMI on 80486SX.
2. Pin A15 is IGNNE on 80486DX. It is not present on 80486SX.
3. C14 is FERR on 80486DX and pins B15 and C14 on 80486SX are not connected.
The architecture of 80486DX is almost the same as that of 80386 except that it contains a math
coprocessor and an 8K byte level 1 cache memory. 80486SX does have the math coprocessor. Figure
13.19 shows the internal architecture of 80486DX. The major difference between 80386 and 80486 is
that almost half of the instructions of 80486 execute in one clocking period instead of the two clocking
periods for the 80386 microprocessor for the same instructions.