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Digital Electronics
Cache
Holding
Register
(CAHR)
Stage
B
Stage
C
Stage
D
Control
Logic
Control
Store
Sequencer and Control
Instruction Pipe
Instruction
Cache
Internal
Data
Bus
Data
Pads
32 Bit
Data
Bus
Size
Multiplexer
Data
Section
Address
Section
Program
Control
Section
Execution Unit
Misalignment
Multiplexer
Instruction
Address
Bus
Address
Pads
Address
Bus
32 Bit
Address
Bus
Write Pending
Buffer
Bus Controller
Prefetch Pending
Buffer
MCAO Bus
Control Logic
Bus Control
Signals
Figure 13.18 Block diagram of 68020.
13.11.3 MC68030 Microprocessor
The MC68030 is a second-generation full 32-bit virtual-memory microprocessor designed using
HCMOS technology (Combining HMOS and CMOS on the same device) from Motorola. It is based
on an MC68020 core with additional features. The MC68030 is a member of the M68000 family of
devices that combines a central processing unit (CPU) core, a data cache, an instruction cache, an
enhanced bus controller and a memory management unit (MMU) in a single VLSI device. It can be
operated at 16.67, 20 and 33 MHz clocks. The MC68030 is upward-object-code compatible with the
earlier members of the M68000 family and has the added features of an on-chip MMU, a data cache