Microprocessors
553
makes up the additional nine addressing modes. These include the direct mode, register indirect
mode, based mode, index mode, scaled index mode, based index mode, based scaled index mode,
based index mode with displacement and based scaled mode with displacement.
13.11.2 MC68020 Microprocessor
This is a 32-bit microprocessor introduced by Motorola. It can execute an object code written for
MC68000, and therefore upward compatibility is maintained. It can operate at 12.5, 16.67, 20, 25 or
33 MHz. The MC68020 is supported by an array of peripheral devices and can directly be interfaced to
coprocessor chips such as the MC68881/MC68882 floating-point and MC68851 memory management
unit (MMU) coprocessor. It can directly address 4 GB of memory. The 68020 microprocessor also
has an on-chip cache of size 128 words (16-bit). It is available in a PGA 114 ceramic-pin grid-array
package and in CQFP 132 (Ceramic Quad Flat Package). Figure 13.18 shows the block diagram of
Motorola’s MC68020.
13.11.2.1 68020 Registers
68020 is a true 32-bit processor and it is object-code compatible with 68000. It has many more registers
than 68000. Besides the eight data registers, seven address registers, one program counter and one
status register (SR), there are three stack pointer (SP) registers instead of two. There is also one 16-bit
vector-based register (VBR), two three-bit function code registers, one 32-bit cache address register
(CAAR) and one 32-bit cache control register (CACR).
13.11.2.2 Instruction set
More than 20 new instructions have been added over MC68000. The new instructions include
some minor improvements and extensions to the supervisor state, several instructions for software
management of a multi-processing system, some support for high-level languages, bigger multiply
(32 × 32) and divide (64/32) instructions and bit field manipulations.
13.11.2.3 Addressing modes
The 68020 microprocessor supports a total of 18 addressing modes with nine basic types:
1. Register direct (data register direct and address register direct).
2. Register indirect (address register indirect, address register indirect with post-increment, address
register indirect with predecrement and address register indirect with displacement).
3. Register address indirect with index (register address indirect with index and register address indirect
with index).
4. Memory indirect (memory indirect post-indexed and memory indirect pre-indexed).
5. Program counter indirect with displacement.
6. Program counter indirect with index (eight-bit displacement and base displacement).
7. Program counter memory indirect (post-indexed, pre-indexed).
8. Absolute data addressing (short and long).
9. Immediate addressing.
553
makes up the additional nine addressing modes. These include the direct mode, register indirect
mode, based mode, index mode, scaled index mode, based index mode, based scaled index mode,
based index mode with displacement and based scaled mode with displacement.
13.11.2 MC68020 Microprocessor
This is a 32-bit microprocessor introduced by Motorola. It can execute an object code written for
MC68000, and therefore upward compatibility is maintained. It can operate at 12.5, 16.67, 20, 25 or
33 MHz. The MC68020 is supported by an array of peripheral devices and can directly be interfaced to
coprocessor chips such as the MC68881/MC68882 floating-point and MC68851 memory management
unit (MMU) coprocessor. It can directly address 4 GB of memory. The 68020 microprocessor also
has an on-chip cache of size 128 words (16-bit). It is available in a PGA 114 ceramic-pin grid-array
package and in CQFP 132 (Ceramic Quad Flat Package). Figure 13.18 shows the block diagram of
Motorola’s MC68020.
13.11.2.1 68020 Registers
68020 is a true 32-bit processor and it is object-code compatible with 68000. It has many more registers
than 68000. Besides the eight data registers, seven address registers, one program counter and one
status register (SR), there are three stack pointer (SP) registers instead of two. There is also one 16-bit
vector-based register (VBR), two three-bit function code registers, one 32-bit cache address register
(CAAR) and one 32-bit cache control register (CACR).
13.11.2.2 Instruction set
More than 20 new instructions have been added over MC68000. The new instructions include
some minor improvements and extensions to the supervisor state, several instructions for software
management of a multi-processing system, some support for high-level languages, bigger multiply
(32 × 32) and divide (64/32) instructions and bit field manipulations.
13.11.2.3 Addressing modes
The 68020 microprocessor supports a total of 18 addressing modes with nine basic types:
1. Register direct (data register direct and address register direct).
2. Register indirect (address register indirect, address register indirect with post-increment, address
register indirect with predecrement and address register indirect with displacement).
3. Register address indirect with index (register address indirect with index and register address indirect
with index).
4. Memory indirect (memory indirect post-indexed and memory indirect pre-indexed).
5. Program counter indirect with displacement.
6. Program counter indirect with index (eight-bit displacement and base displacement).
7. Program counter memory indirect (post-indexed, pre-indexed).
8. Absolute data addressing (short and long).
9. Immediate addressing.