552
Digital Electronics
Request
Prioritizer
Address
Driver
BE0#-BE3#
A2-A31
HOLD, INTR,
NMI, ERROR,
BUSY RESET,
HLDA
Pipeline/
Bus Size
Control
M/IO#, D/C#,
W/R#, LOCK#,
ADS#, NA#,
BS16#, READY#
Multiplexer
Transceivers
D0-D31
Adder
Page
Cache
Control and
Attribute
PLA
l
o
r t
n
o
C
l
a
c i
s
y
h
P s
s
e
r
d
d
A s
u
B
Prefetcher/
Limit Checker
16 Byte Code
Queue
e
g
a
P /
h
c
t
e
F
e
d
o
C h
c
t
e F
e l
b
a
T
3-Input
Adder
Discriptor
Registers
Limit and
Attribute
PLA
Instruction
Decoder
3-Decoded
Instruction
Queue
Code
Stream
32
Instruction
Predecode
Instruction
Prefectch
Internal Control Bus
Control
ROM
Decode and
Sequencing
Register
File
Barrel
Shifter,
Adder
Multiply/
Divide
Protection
Test Unit
Status
Flags
ALU
Control
ALU
Dedicated ALU Bus
Control
Effective Address Bus
Effective Address Bus
Segmentation
Unit
Bus Control
Paging Unit
32
32
32
34
32
s
s
e
r
d
d
A
r
a
e
n i
L s
u
B
32
t
n
e
m
e
c
a
l
p
s
i
D s
u
B
Figure 13.17 Block diagram of the 80386 microprocessor.
4. Logical instructions (Boolean operation, bit test and modify, bit scan, rotate and shift, byte set ON
condition).
5. Control transfer instructions (unconditional transfer, conditional transfer, software-generated
interrupts).
6. String and character translation instructions (repeat prefixes, indexing and direction flag control,
string instructions).
7. Instructions for block-structured languages.
8. Flag control instructions (carry and direction flag control instructions and flag transfer instructions).
9. Coprocessor interface instructions.
10. Segment register instructions (segment register transfer, far-control transfer and data pointer
instructions).
11. Miscellaneous instructions (address calculation, no-operation instruction and translate instruction).
13.11.1.3 Addressing Modes
80386 DX supports a total of 11 addressing modes as follows:
1. Register and immediate modes. These two modes provide for instructions that operate on register
or immediate operands. These include register addressing mode and immediate addressing mode.
2. 32-bit memory addressing modes. The remaining nine modes provide a mechanism for specifying
the effective address of an operand. Here, the effective address is calculated by using combinations
of displacement, base, index and scale address elements. The combination of these four elements
Digital Electronics
Request
Prioritizer
Address
Driver
BE0#-BE3#
A2-A31
HOLD, INTR,
NMI, ERROR,
BUSY RESET,
HLDA
Pipeline/
Bus Size
Control
M/IO#, D/C#,
W/R#, LOCK#,
ADS#, NA#,
BS16#, READY#
Multiplexer
Transceivers
D0-D31
Adder
Page
Cache
Control and
Attribute
PLA
l
o
r t
n
o
C
l
a
c i
s
y
h
P s
s
e
r
d
d
A s
u
B
Prefetcher/
Limit Checker
16 Byte Code
Queue
e
g
a
P /
h
c
t
e
F
e
d
o
C h
c
t
e F
e l
b
a
T
3-Input
Adder
Discriptor
Registers
Limit and
Attribute
PLA
Instruction
Decoder
3-Decoded
Instruction
Queue
Code
Stream
32
Instruction
Predecode
Instruction
Prefectch
Internal Control Bus
Control
ROM
Decode and
Sequencing
Register
File
Barrel
Shifter,
Adder
Multiply/
Divide
Protection
Test Unit
Status
Flags
ALU
Control
ALU
Dedicated ALU Bus
Control
Effective Address Bus
Effective Address Bus
Segmentation
Unit
Bus Control
Paging Unit
32
32
32
34
32
s
s
e
r
d
d
A
r
a
e
n i
L s
u
B
32
t
n
e
m
e
c
a
l
p
s
i
D s
u
B
Figure 13.17 Block diagram of the 80386 microprocessor.
4. Logical instructions (Boolean operation, bit test and modify, bit scan, rotate and shift, byte set ON
condition).
5. Control transfer instructions (unconditional transfer, conditional transfer, software-generated
interrupts).
6. String and character translation instructions (repeat prefixes, indexing and direction flag control,
string instructions).
7. Instructions for block-structured languages.
8. Flag control instructions (carry and direction flag control instructions and flag transfer instructions).
9. Coprocessor interface instructions.
10. Segment register instructions (segment register transfer, far-control transfer and data pointer
instructions).
11. Miscellaneous instructions (address calculation, no-operation instruction and translate instruction).
13.11.1.3 Addressing Modes
80386 DX supports a total of 11 addressing modes as follows:
1. Register and immediate modes. These two modes provide for instructions that operate on register
or immediate operands. These include register addressing mode and immediate addressing mode.
2. 32-bit memory addressing modes. The remaining nine modes provide a mechanism for specifying
the effective address of an operand. Here, the effective address is calculated by using combinations
of displacement, base, index and scale address elements. The combination of these four elements