556
Digital Electronics
32-bit Data Bus
Paging
Unit
Bus
Interface
ALU
Prefetcher
32-bit Data Bus
64-bit interunit transfer bus
Barrel
Shifter
Register
file
Base/
Index
Bus
32
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
Translation
Buffer
Physical
Address
20
2
PCO, PWT
Cache
Unit
8k-byte
Cache
32
32
32
128
32 byte
Code
Queue
2x16 bytes
Code
stream
32
24
Displacement bus
Instruction
Decode
Floating
Point
Unit
Floating
Point
Register
File
Microinstruction
Control and
Protection
Test Unit
Control
ROM
Decoded
Instruction
Path
32
Linear Address Bus
D0-D31
Address
Drivers
Write
Buffers (4x32)
Data Bus
Transceivers
Bus Control
Request
Sequencer
Burst Bus
Control
Bus Size
Control
Cache
Control
Parity generation
and control
Boundary scan
control
TCK, TD1,
TD0, TMS
PCHK#,
DP0-DP3
KEN#,FLUSH#,
AHOLD,EADS#
BS16#Bs8#
BRDY#,
BLAST#
ADS#,W/R#,D/C#, M/IO#,
PCD,PWT,RDY#,LOCK#,
PLOCK#, BOFF#, A20M#,BREQ,
HOLD, HLDA, RESET, SRESET,
INTR,NMI,FERR#,
IGNNE#, STPCLK#
A2-A31,
BE0#-BE3#
Clock
Multiplier
Figure 13.19 Internal architecture of 80486DX.
13.11.4.1 80486DX instruction set
The instruction set can be divided into 11 categories including data transfer operations, arithmetic
operations, shift/rotate instructions, bit manipulation instructions, string manipulation instructions,
control transfer instructions, high-level language support instructions, operating system support
instructions, floating point processor control instructions and floating-point control instructions
13.11.4.2 80486DX registers
It contains all the registers of the 80386 microprocessor and 80386 math coprocessor. The register set is
divided into the following categories: base architecture registers, general-purpose registers, instruction
pointers, flag registers, segment registers, systems-level registers, control registers, system address
registers, floating-point registers, data registers, tag word, status word, instruction and data pointers
and control word and debug and test registers.
13.11.4.3 80486DX operating modes
The operating mode of the 80486 processor determines which instructions and architectural features
are accessible. The 80486 has three modes for running programs. These are as follows:
1. The protected mode uses the native 32-bit instruction set of the processor. In this mode, all
instructions and architectural features are available.
Digital Electronics
32-bit Data Bus
Paging
Unit
Bus
Interface
ALU
Prefetcher
32-bit Data Bus
64-bit interunit transfer bus
Barrel
Shifter
Register
file
Base/
Index
Bus
32
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
Translation
Buffer
Physical
Address
20
2
PCO, PWT
Cache
Unit
8k-byte
Cache
32
32
32
128
32 byte
Code
Queue
2x16 bytes
Code
stream
32
24
Displacement bus
Instruction
Decode
Floating
Point
Unit
Floating
Point
Register
File
Microinstruction
Control and
Protection
Test Unit
Control
ROM
Decoded
Instruction
Path
32
Linear Address Bus
D0-D31
Address
Drivers
Write
Buffers (4x32)
Data Bus
Transceivers
Bus Control
Request
Sequencer
Burst Bus
Control
Bus Size
Control
Cache
Control
Parity generation
and control
Boundary scan
control
TCK, TD1,
TD0, TMS
PCHK#,
DP0-DP3
KEN#,FLUSH#,
AHOLD,EADS#
BS16#Bs8#
BRDY#,
BLAST#
ADS#,W/R#,D/C#, M/IO#,
PCD,PWT,RDY#,LOCK#,
PLOCK#, BOFF#, A20M#,BREQ,
HOLD, HLDA, RESET, SRESET,
INTR,NMI,FERR#,
IGNNE#, STPCLK#
A2-A31,
BE0#-BE3#
Clock
Multiplier
Figure 13.19 Internal architecture of 80486DX.
13.11.4.1 80486DX instruction set
The instruction set can be divided into 11 categories including data transfer operations, arithmetic
operations, shift/rotate instructions, bit manipulation instructions, string manipulation instructions,
control transfer instructions, high-level language support instructions, operating system support
instructions, floating point processor control instructions and floating-point control instructions
13.11.4.2 80486DX registers
It contains all the registers of the 80386 microprocessor and 80386 math coprocessor. The register set is
divided into the following categories: base architecture registers, general-purpose registers, instruction
pointers, flag registers, segment registers, systems-level registers, control registers, system address
registers, floating-point registers, data registers, tag word, status word, instruction and data pointers
and control word and debug and test registers.
13.11.4.3 80486DX operating modes
The operating mode of the 80486 processor determines which instructions and architectural features
are accessible. The 80486 has three modes for running programs. These are as follows:
1. The protected mode uses the native 32-bit instruction set of the processor. In this mode, all
instructions and architectural features are available.