Data Conversion Circuits – D/A and A/D Converters
519
8 Analog
Inputs
8 Channels
Multiplexing
Analog
Switches
TriState
Output
Latch
Buffer
S.A.R
Control&
Timming
Switch
Tree
256R Resistor
Ladder
Clock
Start
Comparator
Address
Latch
And
Decoder
8-Bit A/D
V CC GND REF(+)
REF(-)
Output
Enable
End Of Conversion
(Interrupt)
8-Bit
Outputs
8-Bit
Address
Address
Latch Enable
Figure 12.46 Internal architecture/pin connection diagram of AD 7820.
OSC1
OSC2
OSC3
Test
Ref HI
Ref LO
C +
REF
C REF
Common
IN HI
IN LO
A/Z
Buff
INT
V
G(TENS)
C3
A3
G3
BP/GND
−
−
V +
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
(1000) AB4
POL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
ICL7106(LCD)
ICL7107(LED)
(7106)(7107)
(MINUS)
Figure 12.47 Pin connection diagram of ICL 7106/7107.
519
8 Analog
Inputs
8 Channels
Multiplexing
Analog
Switches
TriState
Output
Latch
Buffer
S.A.R
Control&
Timming
Switch
Tree
256R Resistor
Ladder
Clock
Start
Comparator
Address
Latch
And
Decoder
8-Bit A/D
V CC GND REF(+)
REF(-)
Output
Enable
End Of Conversion
(Interrupt)
8-Bit
Outputs
8-Bit
Address
Address
Latch Enable
Figure 12.46 Internal architecture/pin connection diagram of AD 7820.
OSC1
OSC2
OSC3
Test
Ref HI
Ref LO
C +
REF
C REF
Common
IN HI
IN LO
A/Z
Buff
INT
V
G(TENS)
C3
A3
G3
BP/GND
−
−
V +
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
(1000) AB4
POL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
ICL7106(LCD)
ICL7107(LED)
(7106)(7107)
(MINUS)
Figure 12.47 Pin connection diagram of ICL 7106/7107.
