Data Conversion Circuits – D/A and A/D Converters
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conversion speed at the cost of added complexity. Increase in conversion speed is accomplished
by carrying out integration from reference voltage at two distinct rates, a high-speed rate and a
low-speed rate. The counter is also divided into two sections, one for MSB bits and the other for
LSB bits. A properly designed triple-slope converter achieves increased conversion speed without
compromising the inherent linearity, differential linearity and stability characteristics of the dual-slope
converter.
Bias currents, offset voltages and gain errors associated with operational amplifiers used as integrators
and comparators do introduce some errors. These can be cancelled by using additional charge/discharge
cycles and then using the results to correct the initial measurement. One such A/D converter is the
quad-slope converter which uses two charge/discharge cycles as compared with one charge/discharge
cycle in the case of the dual-slope converter. Quad-slope A/D converters have a much higher accuracy
than their dual-slope counterparts.
12.11.7 Sigma-Delta A/D Converter
The sigma-delta A/D converter employs a different concept from what has been discussed so far for the
case of various types of A/D converter. While the A/D converters covered so far rely on sampling of
the analogue signal at the Nyquist frequency and encode the absolute value of the sample, in the case of
a sigma-delta converter, as explained in the following paragraphs, the analogue signal is oversampled
by a large factor (i.e. the sampling frequency is much larger than the Nyquist value), and also it is
not the absolute value of the sample but the difference between the analogue values of two successive
samples that is encoded by the converter.
In the case of the A/D converters discussed prior to this and sampled at the Nyquist rate f s , the
RMS value of the quantization noise is uniformly distributed over the Nyquist band of DC to f s /2, as
shown in Fig. 12.38(a). The signal-to-noise ratio for a full-scale sine wave input in this case is given by
S/N = (6.02n + 1.76) dB, n being the number of bits. The only way to increase the signal-to-noise ratio
is by increasing the number of bits. On the other hand, a sigma-delta converter attempts to enhance the
signal-to-noise ratio by oversampling the analogue signal, which has the effect of spreading the noise
spectrum over a much larger bandwidth and then filtering out the desired band. If the analogue signal
were sampled at a rate of Kf s , the quantization noise would be spread over DC to Kf s /2, as shown in
Fig. 12.38(b). K is a constant referred to as the oversampling ratio. The enhanced S/N ratio means
higher resolution, which is achieved by other types of A/D converter by way of increasing the number
of bits.
It may be mentioned here that, if we simply use oversampling to improve the resolution, it would be
required to oversample by a factor of 2
2N to achieve an N -bit increase in resolution. The sigma-delta
converter does not require to be oversampled by such a large factor because it not only limits the
signal pass band but also shapes the quantization noise in such a way that most of it falls outside this
pass band, as shown in Fig. 12.38(c). The following paragraphs explain the operational principle of
the sigma-delta A/D converter.
The heart of the sigma-delta converter is the delta modulator. Figure 12.39 shows a block schematic
representation of a delta modulator, which is basically a one-bit quantizer of the flash type (single
comparator). The output of the delta modulator is a bit stream of 1s and 0s, with the number of 1s
relative to the number of 0s over a given number of clock cycles indicating the amplitude of the
analogue signal over that time interval. An all 1s sequence over a given interval corresponds to the
maximum positive amplitude, and an all 0s sequence indicates the maximum negative amplitude. An
equal number of 1s and 0s indicates a zero amplitude. Other values between the positive and negative
maxima are indicated by a proportional number of 1s relative to the number of 0s. This is further
illustrated in Fig. 12.40.
509
conversion speed at the cost of added complexity. Increase in conversion speed is accomplished
by carrying out integration from reference voltage at two distinct rates, a high-speed rate and a
low-speed rate. The counter is also divided into two sections, one for MSB bits and the other for
LSB bits. A properly designed triple-slope converter achieves increased conversion speed without
compromising the inherent linearity, differential linearity and stability characteristics of the dual-slope
converter.
Bias currents, offset voltages and gain errors associated with operational amplifiers used as integrators
and comparators do introduce some errors. These can be cancelled by using additional charge/discharge
cycles and then using the results to correct the initial measurement. One such A/D converter is the
quad-slope converter which uses two charge/discharge cycles as compared with one charge/discharge
cycle in the case of the dual-slope converter. Quad-slope A/D converters have a much higher accuracy
than their dual-slope counterparts.
12.11.7 Sigma-Delta A/D Converter
The sigma-delta A/D converter employs a different concept from what has been discussed so far for the
case of various types of A/D converter. While the A/D converters covered so far rely on sampling of
the analogue signal at the Nyquist frequency and encode the absolute value of the sample, in the case of
a sigma-delta converter, as explained in the following paragraphs, the analogue signal is oversampled
by a large factor (i.e. the sampling frequency is much larger than the Nyquist value), and also it is
not the absolute value of the sample but the difference between the analogue values of two successive
samples that is encoded by the converter.
In the case of the A/D converters discussed prior to this and sampled at the Nyquist rate f s , the
RMS value of the quantization noise is uniformly distributed over the Nyquist band of DC to f s /2, as
shown in Fig. 12.38(a). The signal-to-noise ratio for a full-scale sine wave input in this case is given by
S/N = (6.02n + 1.76) dB, n being the number of bits. The only way to increase the signal-to-noise ratio
is by increasing the number of bits. On the other hand, a sigma-delta converter attempts to enhance the
signal-to-noise ratio by oversampling the analogue signal, which has the effect of spreading the noise
spectrum over a much larger bandwidth and then filtering out the desired band. If the analogue signal
were sampled at a rate of Kf s , the quantization noise would be spread over DC to Kf s /2, as shown in
Fig. 12.38(b). K is a constant referred to as the oversampling ratio. The enhanced S/N ratio means
higher resolution, which is achieved by other types of A/D converter by way of increasing the number
of bits.
It may be mentioned here that, if we simply use oversampling to improve the resolution, it would be
required to oversample by a factor of 2
2N to achieve an N -bit increase in resolution. The sigma-delta
converter does not require to be oversampled by such a large factor because it not only limits the
signal pass band but also shapes the quantization noise in such a way that most of it falls outside this
pass band, as shown in Fig. 12.38(c). The following paragraphs explain the operational principle of
the sigma-delta A/D converter.
The heart of the sigma-delta converter is the delta modulator. Figure 12.39 shows a block schematic
representation of a delta modulator, which is basically a one-bit quantizer of the flash type (single
comparator). The output of the delta modulator is a bit stream of 1s and 0s, with the number of 1s
relative to the number of 0s over a given number of clock cycles indicating the amplitude of the
analogue signal over that time interval. An all 1s sequence over a given interval corresponds to the
maximum positive amplitude, and an all 0s sequence indicates the maximum negative amplitude. An
equal number of 1s and 0s indicates a zero amplitude. Other values between the positive and negative
maxima are indicated by a proportional number of 1s relative to the number of 0s. This is further
illustrated in Fig. 12.40.