Data Conversion Circuits – D/A and A/D Converters
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added to the converter. Thus, the resolution can be improved only at the cost of a longer conversion
time. This makes the counter-type A/D converter unsuitable for digitizing rapidly changing analogue
signals.
12.11.4 Tracking-Type A/D Converter
In the counter-type A/D converter described above, the counter is reset to zero at the start of each
new conversion. The D/A converter output staircase waveform always begins at zero and increases in
steps until it reaches a point where the analogue output of the D/A converter exceeds the analogue
input to be digitized. As a result, the counter-type A/D converter of the type discussed above is slow.
The tracking-type A/D converter, also called the delta-encoded A/D converter, is a modified form of
counter-type converter that to some extent overcomes the shortcoming of the latter. In the modified
arrangement, the counter, which is primarily an UP counter, is replaced with an UP/DOWN counter.
It counts in upward sequence whenever the D/A converter output analogue voltage is less than the
analogue input voltage to be digitized, and it counts in the downward sequence whenever the D/A
converter output analogue voltage is greater than the analogue input voltage. In this type of converter,
whenever a new conversion is to begin, the counter is not reset to zero; in fact it begins counting either
up or down from its last value, depending upon the comparator output. The D/A converter output
staircase waveform contains both positive-going and negative-going staircase signals that track the
input analogue signal.
12.11.5 Successive Approximation Type A/D Converter
The development of A/D converters has progressed in a quest to reduce the conversion time. The
successive approximation type A/D converter aims at approximating the analogue signal to be digitized
by trying only one bit at a time. The process of A/D conversion by this technique can be illustrated
with the help of an example. Let us take a four-bit successive approximation type A/D converter.
Initially, the counter is reset to all 0s. The conversion process begins with the MSB being set by the
start pulse. That is, the flip-flop representing the MSB is set. The counter output is converted into an
equivalent analogue signal and then compared with the analogue signal to be digitized. A decision is
then taken as to whether the MSB is to be left in (i.e. the flip-flop representing the MSB is to remain
set) or whether it is to be taken out (i.e. the flip-flop is to be reset) when the first clock pulse sets
the second MSB. Once the second MSB is set, again a comparison is made and a decision taken as to
whether or not the second MSB is to remain set when the subsequent clock pulse sets the third MSB.
The process continues until we go down to the LSB. Note that, every time we make a comparison,
we tend to narrow down the difference between the analogue signal to be digitized and the analogue
signal representing the counter count. Refer to the operational diagram of Fig. 12.33. It is clear from
the diagram that, to reach any count from 0000 to 1111, the converter requires four clock cycles. In
general, the number of clock cycles required for each conversion will be n for an n-bit A/D converter
of this type.
Figure 12.34 shows a block schematic representation of a successive approximation type A/D
converter. Since only one flip-flop (in the counter) is operated upon at one time, a ring counter, which
is nothing but a circulating register (a serial shift register with the outputs Q and Q of the last flip-flop
connected to the J and K inputs respectively of the first flip-flop), is used to do the job. Referring to
Fig. 12.33, the dark lines show the sequence in which the counter arrives at the desired count, assuming
that 1001 is the desired count. This type of A/D converter is much faster than the counter-type A/D
converter previously discussed. In an n-bit converter, the counter-type A/D converter on average would
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added to the converter. Thus, the resolution can be improved only at the cost of a longer conversion
time. This makes the counter-type A/D converter unsuitable for digitizing rapidly changing analogue
signals.
12.11.4 Tracking-Type A/D Converter
In the counter-type A/D converter described above, the counter is reset to zero at the start of each
new conversion. The D/A converter output staircase waveform always begins at zero and increases in
steps until it reaches a point where the analogue output of the D/A converter exceeds the analogue
input to be digitized. As a result, the counter-type A/D converter of the type discussed above is slow.
The tracking-type A/D converter, also called the delta-encoded A/D converter, is a modified form of
counter-type converter that to some extent overcomes the shortcoming of the latter. In the modified
arrangement, the counter, which is primarily an UP counter, is replaced with an UP/DOWN counter.
It counts in upward sequence whenever the D/A converter output analogue voltage is less than the
analogue input voltage to be digitized, and it counts in the downward sequence whenever the D/A
converter output analogue voltage is greater than the analogue input voltage. In this type of converter,
whenever a new conversion is to begin, the counter is not reset to zero; in fact it begins counting either
up or down from its last value, depending upon the comparator output. The D/A converter output
staircase waveform contains both positive-going and negative-going staircase signals that track the
input analogue signal.
12.11.5 Successive Approximation Type A/D Converter
The development of A/D converters has progressed in a quest to reduce the conversion time. The
successive approximation type A/D converter aims at approximating the analogue signal to be digitized
by trying only one bit at a time. The process of A/D conversion by this technique can be illustrated
with the help of an example. Let us take a four-bit successive approximation type A/D converter.
Initially, the counter is reset to all 0s. The conversion process begins with the MSB being set by the
start pulse. That is, the flip-flop representing the MSB is set. The counter output is converted into an
equivalent analogue signal and then compared with the analogue signal to be digitized. A decision is
then taken as to whether the MSB is to be left in (i.e. the flip-flop representing the MSB is to remain
set) or whether it is to be taken out (i.e. the flip-flop is to be reset) when the first clock pulse sets
the second MSB. Once the second MSB is set, again a comparison is made and a decision taken as to
whether or not the second MSB is to remain set when the subsequent clock pulse sets the third MSB.
The process continues until we go down to the LSB. Note that, every time we make a comparison,
we tend to narrow down the difference between the analogue signal to be digitized and the analogue
signal representing the counter count. Refer to the operational diagram of Fig. 12.33. It is clear from
the diagram that, to reach any count from 0000 to 1111, the converter requires four clock cycles. In
general, the number of clock cycles required for each conversion will be n for an n-bit A/D converter
of this type.
Figure 12.34 shows a block schematic representation of a successive approximation type A/D
converter. Since only one flip-flop (in the counter) is operated upon at one time, a ring counter, which
is nothing but a circulating register (a serial shift register with the outputs Q and Q of the last flip-flop
connected to the J and K inputs respectively of the first flip-flop), is used to do the job. Referring to
Fig. 12.33, the dark lines show the sequence in which the counter arrives at the desired count, assuming
that 1001 is the desired count. This type of A/D converter is much faster than the counter-type A/D
converter previously discussed. In an n-bit converter, the counter-type A/D converter on average would