Counters and Registers
467
(9)
CLK
C1/
SRG8
(11)
B
(12)
A
&
1 D
(14)
QH
(13) QH
(a)
(3)
Q A
(1)
A
&
(9)
(8)
CLR
CLK
SRG8
(2)
B
1D
(5)
Q C
(6)
Q D
(10)
Q E
(11)
Q F
(12)
Q G
(13)
(4)
Q B
Q H
C1/
(b)
R
Figure 11.53 IEEE/ANSI notation for (a) IC 7491 and (b) IC 74164.
3. Briefly describe:
(a) how the architecture of an asynchronous UP counter differs from that of a DOWN counter;
(b) how the architecture of a ring counter differs from that of a shift counter.
4. Briefly explain why the maximum usable clock frequency of a ripple counter decreases as more
flip-flops are added to the counter to increase its MOD-number.
5. Why is the maximum usable clock frequency in the case of a synchronous counter independent of
the size of counter?
6. How can presettable counters be used to construct counters with variable modulus?