466
Digital Electronics
reset (MR) input implies that the counter is reset to all 0s when the MR input is in the logic HIGH
state. Label C3 with parallel load (PL) input means that the data on parallel load inputs P 0 , P 1 , P 2 and
P 3 are loaded onto the corresponding flip-flops when the PL input is in the logic LOW state. We can
see the prefix 3 in the labels of the flip-flops. The CPU input has an AND dependency with the TCU
output and CPD input. In the case of the former, the TCU output goes to the logic LOW state when
the CPU is LOW and the count reaches ‘15’. In the case of the latter, the CPU input should be in
the logic HIGH state in order to allow the CPD to perform the count DOWN function. Similarly, the
CPD input has an AND dependency with the TCD output and CPU input. In the case of the former,
the TCD output goes to the logic LOW state when the CPD is LOW and the count reaches ‘0’. In
the case of the latter, the CPD input should be in the logic HIGH state in order to allow the CPU to
perform the count UP function.
11.14.2 Registers
As an illustration, we will consider IEEE/ANSI symbols of a serial-in serial-out shift register, type
number 7491, and a serial-in parallel-out shift register, type number 74164. Figures 11.53(a) and (b)
show the IEEE/ANSI notations for IC 7491 and IC 74164 respectively.
We will begin with shift register type number 7491. Label SRG8 stands for eight-bit shift register.
Label C1/→ with the clock input means that the relevant clock transition performs two functions.
Firstly, it loads data onto the data input as indicated by prefix ‘1’ with the D input. Secondly, it
performs a right shift operation. The A and B inputs have an AND dependency. When data are entered
through either of the two inputs, the other input must be held in the logic HIGH state to allow the data
bit to be loaded onto the data input terminal.
We will now consider shift register type number 74164. Label ‘R’ stands for reset operation.
Whenever the MR input is driven to the logic LOW state, the shift register is reset to all 0s. The rest
of the notations have already been explained in the case of register type number 7491.
11.15 Application-Relevant Information
Table 11.16 lists the commonly used IC counters and registers belonging to the TTL, CMOS and
ECL logic families. Application-relevant information on more popular type numbers is given in the
companion website. The information includes the pin configuration diagram, functional table and
timing waveforms in some cases.
Review Questions
1. Differentiate between:
(a) asynchronous and synchronous counters;
(b) UP, DOWN and UP/DOWN counters;
(c) presettable and clearable counters;
(d) BCD and decade counters.
2. Indicate the difference between the counting sequences of:
(a) a four-bit binary UP counter and a four-bit binary DOWN counter;
(b) a four-bit ring counter and a four-bit Johnson counter.
Digital Electronics
reset (MR) input implies that the counter is reset to all 0s when the MR input is in the logic HIGH
state. Label C3 with parallel load (PL) input means that the data on parallel load inputs P 0 , P 1 , P 2 and
P 3 are loaded onto the corresponding flip-flops when the PL input is in the logic LOW state. We can
see the prefix 3 in the labels of the flip-flops. The CPU input has an AND dependency with the TCU
output and CPD input. In the case of the former, the TCU output goes to the logic LOW state when
the CPU is LOW and the count reaches ‘15’. In the case of the latter, the CPU input should be in
the logic HIGH state in order to allow the CPD to perform the count DOWN function. Similarly, the
CPD input has an AND dependency with the TCD output and CPU input. In the case of the former,
the TCD output goes to the logic LOW state when the CPD is LOW and the count reaches ‘0’. In
the case of the latter, the CPD input should be in the logic HIGH state in order to allow the CPU to
perform the count UP function.
11.14.2 Registers
As an illustration, we will consider IEEE/ANSI symbols of a serial-in serial-out shift register, type
number 7491, and a serial-in parallel-out shift register, type number 74164. Figures 11.53(a) and (b)
show the IEEE/ANSI notations for IC 7491 and IC 74164 respectively.
We will begin with shift register type number 7491. Label SRG8 stands for eight-bit shift register.
Label C1/→ with the clock input means that the relevant clock transition performs two functions.
Firstly, it loads data onto the data input as indicated by prefix ‘1’ with the D input. Secondly, it
performs a right shift operation. The A and B inputs have an AND dependency. When data are entered
through either of the two inputs, the other input must be held in the logic HIGH state to allow the data
bit to be loaded onto the data input terminal.
We will now consider shift register type number 74164. Label ‘R’ stands for reset operation.
Whenever the MR input is driven to the logic LOW state, the shift register is reset to all 0s. The rest
of the notations have already been explained in the case of register type number 7491.
11.15 Application-Relevant Information
Table 11.16 lists the commonly used IC counters and registers belonging to the TTL, CMOS and
ECL logic families. Application-relevant information on more popular type numbers is given in the
companion website. The information includes the pin configuration diagram, functional table and
timing waveforms in some cases.
Review Questions
1. Differentiate between:
(a) asynchronous and synchronous counters;
(b) UP, DOWN and UP/DOWN counters;
(c) presettable and clearable counters;
(d) BCD and decade counters.
2. Indicate the difference between the counting sequences of:
(a) a four-bit binary UP counter and a four-bit binary DOWN counter;
(b) a four-bit ring counter and a four-bit Johnson counter.