438
Digital Electronics
• A HIGH-to-LOW transition at the TCD output,coinciding with the trailing edge of the sixth clock
pulse, loads 0110 to the counter output.
• Therefore, immediately after the leading edge of the eighth clock pulse, the counter will be in the
0100 state.
11.11 Designing Counters with Arbitrary Sequences
So far we have discussed different types of synchronous and asynchronous counters. A large variety
of synchronous and asynchronous counters are available in IC form, and some of these have been
mentioned and discussed in the previous sections. The counters discussed hitherto count in either the
normal binary sequence with a modulus of 2
N or with slightly altered binary sequences where one or
more of the states are skipped. The latter type of counter has a modulus of less than 2
N , N being the
number of flip-flops used. Nevertheless, even these counters have a sequence that is either upwards or
downwards and not arbitrary. There are applications where a counter is required to follow a sequence
that is arbitrary and not binary. As an example, an MOD-10 counter may be required to follow the
sequence 0000, 0010, 0101, 0001, 0111, 0011, 0100, 1010, 1000, 1111, 0000, 0010 and so on. In such
cases, the simple and seemingly obvious feedback arrangement with a single NAND gate discussed
in the earlier sections of this chapter for designing counters with a modulus of less than 2
N cannot be
used.
There are several techniques for designing counters that follow a given arbitrary sequence. In the
present section, we will discuss in detail a commonly used technique for designing synchronous
counters using J-K flip-flops or D flip-flops. The design of the counters basically involves designing
a suitable combinational logic circuit that takes its inputs from the normal and complemented outputs
of the flip-flops used and decodes the different states of the counter to generate the correct logic states
for the inputs of the flip-flops such as J , K, D, etc. But before we illustrate the design procedure with
the help of an example, we will explain what we mean by the excitation table of a flip-flop and the
state transition diagram of a counter. An excitation table in fact can be drawn for any sequential logic
circuit, but, once we understand what it is in the case of a flip-flop, which is the basic building block
of sequential logic, it would be much easier for us to draw the same for more complex sequential
circuits such as counters, etc.
11.11.1 Excitation Table of a Flip-Flop
The excitation table is similar to the characteristic table that we discussed in the previous chapter on
flip-flops. The excitation table lists the present state, the desired next state and the flip-flop inputs
(J , K, D, etc.) required to achieve that. The same for a J-K flip-flop and a D flip-flop are shown in
Tables 11.7 and 11.8 respectively. Referring to Table 11.7, if the output is in the logic ‘0’ state and it
is desired that it goes to the logic ‘1’ state on occurrence of the clock pulse, the J input must be in
the logic ‘1’ state and the K input can be either in the logic ‘0’ or logic ‘1’ state. This is true as, for
a ‘0’ to ‘1’ transition, there are two possible input conditions that can achieve this. These are J = 1,
K = 0 (SET mode) and J = K = 1 (toggle mode), which further leads to J = 1 K = X (either 0
or 1). The other entries of the excitation table can be explained on similar lines.
In the case of a D flip-flop, the D input is the same as the logic status of the desired next state. This
is true as, in the case of a D flip-flop, the D input is transferred to the output on the occurrence of the
clock pulse, irrespective of the present logic status of the Q output.
Digital Electronics
• A HIGH-to-LOW transition at the TCD output,coinciding with the trailing edge of the sixth clock
pulse, loads 0110 to the counter output.
• Therefore, immediately after the leading edge of the eighth clock pulse, the counter will be in the
0100 state.
11.11 Designing Counters with Arbitrary Sequences
So far we have discussed different types of synchronous and asynchronous counters. A large variety
of synchronous and asynchronous counters are available in IC form, and some of these have been
mentioned and discussed in the previous sections. The counters discussed hitherto count in either the
normal binary sequence with a modulus of 2
N or with slightly altered binary sequences where one or
more of the states are skipped. The latter type of counter has a modulus of less than 2
N , N being the
number of flip-flops used. Nevertheless, even these counters have a sequence that is either upwards or
downwards and not arbitrary. There are applications where a counter is required to follow a sequence
that is arbitrary and not binary. As an example, an MOD-10 counter may be required to follow the
sequence 0000, 0010, 0101, 0001, 0111, 0011, 0100, 1010, 1000, 1111, 0000, 0010 and so on. In such
cases, the simple and seemingly obvious feedback arrangement with a single NAND gate discussed
in the earlier sections of this chapter for designing counters with a modulus of less than 2
N cannot be
used.
There are several techniques for designing counters that follow a given arbitrary sequence. In the
present section, we will discuss in detail a commonly used technique for designing synchronous
counters using J-K flip-flops or D flip-flops. The design of the counters basically involves designing
a suitable combinational logic circuit that takes its inputs from the normal and complemented outputs
of the flip-flops used and decodes the different states of the counter to generate the correct logic states
for the inputs of the flip-flops such as J , K, D, etc. But before we illustrate the design procedure with
the help of an example, we will explain what we mean by the excitation table of a flip-flop and the
state transition diagram of a counter. An excitation table in fact can be drawn for any sequential logic
circuit, but, once we understand what it is in the case of a flip-flop, which is the basic building block
of sequential logic, it would be much easier for us to draw the same for more complex sequential
circuits such as counters, etc.
11.11.1 Excitation Table of a Flip-Flop
The excitation table is similar to the characteristic table that we discussed in the previous chapter on
flip-flops. The excitation table lists the present state, the desired next state and the flip-flop inputs
(J , K, D, etc.) required to achieve that. The same for a J-K flip-flop and a D flip-flop are shown in
Tables 11.7 and 11.8 respectively. Referring to Table 11.7, if the output is in the logic ‘0’ state and it
is desired that it goes to the logic ‘1’ state on occurrence of the clock pulse, the J input must be in
the logic ‘1’ state and the K input can be either in the logic ‘0’ or logic ‘1’ state. This is true as, for
a ‘0’ to ‘1’ transition, there are two possible input conditions that can achieve this. These are J = 1,
K = 0 (SET mode) and J = K = 1 (toggle mode), which further leads to J = 1 K = X (either 0
or 1). The other entries of the excitation table can be explained on similar lines.
In the case of a D flip-flop, the D input is the same as the logic status of the desired next state. This
is true as, in the case of a D flip-flop, the D input is transferred to the output on the occurrence of the
clock pulse, irrespective of the present logic status of the Q output.