Counters and Registers
415
Table 11.1 Output logic states for different clock signal transitions
for a four-bit binary ripple counter.
Clock signal transition number
Q 0
Q 1
Q 2
Q 3
After first clock transition
1
0
0
0
After second clock transition
0
1
0
0
After third clock transition
1
1
0
0
After fourth clock transition
0
0
1
0
After fifth clock transition
1
0
1
0
After sixth clock transition
0
1
1
0
After seventh clock transition
1
1
1
0
After eighth clock transition
0
0
0
1
After ninth clock transition
1
0
0
1
After tenth clock transition
0
1
0
1
After eleventh clock transition
1
1
0
1
After twelfth clock transition
0
0
1
1
After thirteenth clock transition
1
0
1
1
After fourteenth clock transition
0
1
1
1
After fifteenth clock transition
1
1
1
1
After sixteenth clock transition
0
0
0
0
in Fig. 11.2(b), that the frequencies of the Q 0 , Q 1 , Q 2 and Q 3 waveforms are f/2,f/4, f/8 and f/16
respectively. Here, f is the frequency of the clock input. This implies that a counter of this type can be
used as a divide-by-2
N circuit, where N is the number of flip-flops in the counter chain. In fact, such a
counter provides frequency-divided outputs of f/2
N , f/2
N −1 , f/2
N −2 , f/2
N −3 , , f /2 at the outputs
of the N th, (N − 1)th, (N − 2)th, (N − 3)th, , first flip-flops. In the case of a four-bit counter of the
type shown in Fig. 11.2(a), outputs are available at f/2 from the Q 0 output, at f/4 from the Q 1 output,
at f/8 from the Q 2 output and at f/16 from the Q 3 output. It may be noted that frequency division is
one of the major applications of counters.
Example 11.1
A four-bit binary ripple counter of the type shown in Fig. 11.2(a) is initially in the 0000 state before
the clock input is applied to the counter. The clock pulses are applied to the counter at some time
instant t 1 and then again removed some time later at another time instant t 2 . The counter is observed
to read 0011. How many negative-going clock transitions have occurred during the time the clock was
active at the counter input?
Solution
It is not possible to determine the number of clock edges – it could have been 3, 19, 35, 51, 67,
83 – as there is no means of finding out whether the counter has recycled or not from the
given data. Remember that this counter would come back to the 0000 state after every 16 clock
pulses.
415
Table 11.1 Output logic states for different clock signal transitions
for a four-bit binary ripple counter.
Clock signal transition number
Q 0
Q 1
Q 2
Q 3
After first clock transition
1
0
0
0
After second clock transition
0
1
0
0
After third clock transition
1
1
0
0
After fourth clock transition
0
0
1
0
After fifth clock transition
1
0
1
0
After sixth clock transition
0
1
1
0
After seventh clock transition
1
1
1
0
After eighth clock transition
0
0
0
1
After ninth clock transition
1
0
0
1
After tenth clock transition
0
1
0
1
After eleventh clock transition
1
1
0
1
After twelfth clock transition
0
0
1
1
After thirteenth clock transition
1
0
1
1
After fourteenth clock transition
0
1
1
1
After fifteenth clock transition
1
1
1
1
After sixteenth clock transition
0
0
0
0
in Fig. 11.2(b), that the frequencies of the Q 0 , Q 1 , Q 2 and Q 3 waveforms are f/2,f/4, f/8 and f/16
respectively. Here, f is the frequency of the clock input. This implies that a counter of this type can be
used as a divide-by-2
N circuit, where N is the number of flip-flops in the counter chain. In fact, such a
counter provides frequency-divided outputs of f/2
N , f/2
N −1 , f/2
N −2 , f/2
N −3 , , f /2 at the outputs
of the N th, (N − 1)th, (N − 2)th, (N − 3)th, , first flip-flops. In the case of a four-bit counter of the
type shown in Fig. 11.2(a), outputs are available at f/2 from the Q 0 output, at f/4 from the Q 1 output,
at f/8 from the Q 2 output and at f/16 from the Q 3 output. It may be noted that frequency division is
one of the major applications of counters.
Example 11.1
A four-bit binary ripple counter of the type shown in Fig. 11.2(a) is initially in the 0000 state before
the clock input is applied to the counter. The clock pulses are applied to the counter at some time
instant t 1 and then again removed some time later at another time instant t 2 . The counter is observed
to read 0011. How many negative-going clock transitions have occurred during the time the clock was
active at the counter input?
Solution
It is not possible to determine the number of clock edges – it could have been 3, 19, 35, 51, 67,
83 – as there is no means of finding out whether the counter has recycled or not from the
given data. Remember that this counter would come back to the 0000 state after every 16 clock
pulses.