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Digital Electronics
Example 11.2
It is desired to design a binary ripple counter of the type shown in Fig. 11.1 that is capable of counting
the number of items passing on a conveyor belt. Each time an item passes a given point, a pulse is
generated that can be used as a clock input. If the maximum number of items to be counted is 6000,
determine the number of flip-flops required.
Solution
• The counter should be able to count a maximum of 6000 items.
• An N -flip-flop would be able to count up to a maximum of 2
N
− 1 counts.
• On the 2
N th clock pulse, it will get reset to all 0s.
• Now, 2
N
− 1 should be greater than or equal to 6000.
• That is, 2
N
− 1 ≥ 6000, which gives N ≥ log 6001/log 2 ≥ 3.778/0.3010 ≥ 12.55.
• The smallest integer that satisfies this condition is 13.
• Therefore, the minimum number of flip-flops required = 13
11.4.1 Binary Ripple Counters with a Modulus of Less than 2
N
An N -flip-flop binary ripple counter can be modified, as we will see in the following paragraphs, to
have any other modulus less than 2
N with the help of simple externally connected combinational logic.
We will illustrate this simple concept with the help of an example.
Consider the four-flip-flop binary ripple counter arrangement of Fig. 11.3(a). It uses J-K flip-flops
with an active LOW asynchronous CLEAR input. The NAND gate in the figure has its output connected
to the CLEAR inputs of all four flip-flops. The inputs to this three-input NAND gate are from the Q
outputs of flip-flops FF0, FF1 and FF2. If we disregard the NAND gate for some time, this counter
will go through its natural binary sequence from 0000 to 1111. But that is not to happen in the present
arrangement. The counter does start counting from 0000 towards its final count of 1111. The counter
keeps counting as long as the asynchronous CLEAR inputs of the different flip-flops are inactive. That
is, the NAND gate output is HIGH. This is the case until the counter reaches 0110. With the seventh
clock pulse it tends to go to 0111, which makes all NAND gate inputs HIGH, forcing its output to
LOW. This HIGH-to-LOW transition at the NAND gate output clears all flip-flop outputs to the logic
‘0’ state, thus disallowing the counter to settle at 0111. From the eighth clock pulse onwards, the
counter repeats the sequence. The counter thus always counts from 0000 to 0110 and resets back to
0000. The remaining nine states, which include 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 and
1111, are skipped, with the result that we get an MOD-7 counter.
Figure 11.3(b) shows the timing waveforms for this counter. By suitably choosing NAND inputs,
one can get a counter with any MOD number less than 16. Examination of timing waveforms also
reveals that the frequency of the Q 2 output is one-seventh of the input clock frequency.
The waveform at the Q 2 output is, however, not symmetrical as it would be if the counter were to
go through its full binary sequence. The Q 3 output stays in the logic LOW state. It is expected to be
so because an MOD-7 counter needs a minimum of three flip-flops. That is why the fourth flip-flop,
which was supposed to toggle on the HIGH-to-LOW transition of the eighth clock pulse, and on every
successive eighth pulse thereafter, never gets to that stage. The counter is cleared on the seventh clock
pulse and every successive seventh clock pulse thereafter.
As another illustration, if the NAND gate used in the counter arrangement of Fig. 11.3(a) is a
two-input NAND and its inputs are from the Q 1 and Q 3 outputs, the counter will go through 0000 to
1001 and then reset to 0000 again, as, the moment the counter tends to switch from the 1001 to the
1010 state, the NAND gate goes from the ‘1’ to the ‘0’ state, clearing all flip-flops to the ‘0’ state.
Digital Electronics
Example 11.2
It is desired to design a binary ripple counter of the type shown in Fig. 11.1 that is capable of counting
the number of items passing on a conveyor belt. Each time an item passes a given point, a pulse is
generated that can be used as a clock input. If the maximum number of items to be counted is 6000,
determine the number of flip-flops required.
Solution
• The counter should be able to count a maximum of 6000 items.
• An N -flip-flop would be able to count up to a maximum of 2
N
− 1 counts.
• On the 2
N th clock pulse, it will get reset to all 0s.
• Now, 2
N
− 1 should be greater than or equal to 6000.
• That is, 2
N
− 1 ≥ 6000, which gives N ≥ log 6001/log 2 ≥ 3.778/0.3010 ≥ 12.55.
• The smallest integer that satisfies this condition is 13.
• Therefore, the minimum number of flip-flops required = 13
11.4.1 Binary Ripple Counters with a Modulus of Less than 2
N
An N -flip-flop binary ripple counter can be modified, as we will see in the following paragraphs, to
have any other modulus less than 2
N with the help of simple externally connected combinational logic.
We will illustrate this simple concept with the help of an example.
Consider the four-flip-flop binary ripple counter arrangement of Fig. 11.3(a). It uses J-K flip-flops
with an active LOW asynchronous CLEAR input. The NAND gate in the figure has its output connected
to the CLEAR inputs of all four flip-flops. The inputs to this three-input NAND gate are from the Q
outputs of flip-flops FF0, FF1 and FF2. If we disregard the NAND gate for some time, this counter
will go through its natural binary sequence from 0000 to 1111. But that is not to happen in the present
arrangement. The counter does start counting from 0000 towards its final count of 1111. The counter
keeps counting as long as the asynchronous CLEAR inputs of the different flip-flops are inactive. That
is, the NAND gate output is HIGH. This is the case until the counter reaches 0110. With the seventh
clock pulse it tends to go to 0111, which makes all NAND gate inputs HIGH, forcing its output to
LOW. This HIGH-to-LOW transition at the NAND gate output clears all flip-flop outputs to the logic
‘0’ state, thus disallowing the counter to settle at 0111. From the eighth clock pulse onwards, the
counter repeats the sequence. The counter thus always counts from 0000 to 0110 and resets back to
0000. The remaining nine states, which include 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 and
1111, are skipped, with the result that we get an MOD-7 counter.
Figure 11.3(b) shows the timing waveforms for this counter. By suitably choosing NAND inputs,
one can get a counter with any MOD number less than 16. Examination of timing waveforms also
reveals that the frequency of the Q 2 output is one-seventh of the input clock frequency.
The waveform at the Q 2 output is, however, not symmetrical as it would be if the counter were to
go through its full binary sequence. The Q 3 output stays in the logic LOW state. It is expected to be
so because an MOD-7 counter needs a minimum of three flip-flops. That is why the fourth flip-flop,
which was supposed to toggle on the HIGH-to-LOW transition of the eighth clock pulse, and on every
successive eighth pulse thereafter, never gets to that stage. The counter is cleared on the seventh clock
pulse and every successive seventh clock pulse thereafter.
As another illustration, if the NAND gate used in the counter arrangement of Fig. 11.3(a) is a
two-input NAND and its inputs are from the Q 1 and Q 3 outputs, the counter will go through 0000 to
1001 and then reset to 0000 again, as, the moment the counter tends to switch from the 1001 to the
1010 state, the NAND gate goes from the ‘1’ to the ‘0’ state, clearing all flip-flops to the ‘0’ state.