Counters and Registers
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ripple counter from this logic family can not be clocked faster than 10 MHz. The upper limit on the
clock frequency further decreases with increase in the number of bits to be handled by the counter.
11.2 Synchronous Counter
In a synchronous counter, also known as a parallel counter, all the flip-flops in the counter change
state at the same time in synchronism with the input clock signal. The clock signal in this case is
simultaneously applied to the clock inputs of all the flip-flops. The delay involved in this case is equal
to the propagation delay of one flip-flop only, irrespective of the number of flip-flops used to construct
the counter. In other words, the delay is independent of the size of the counter.
11.3 Modulus of a Counter
The modulus (MOD number) of a counter is the number of different logic states it goes through before
it comes back to the initial state to repeat the count sequence. An n-bit counter that counts through
all its natural states and does not skip any of the states has a modulus of 2
n . We can see that such
counters have a modulus that is an integral power of 2, that is, 2, 4, 8, 16 and so on. These can be
modified with the help of additional combinational logic to get a modulus of less than 2
n .
To determine the number of flip-flops required to build a counter having a given modulus, identify
the smallest integer m that is either equal to or greater than the desired modulus and is also equal
to an integral power of 2. For instance, if the desired modulus is 10, which is the case in a decade
counter, the smallest integer greater than or equal to 10 and which is also an integral power of 2 is
16. The number of flip-flops in this case would be 4, as 16 = 2
4 . On the same lines, the number of
flip-flops required to construct counters with MOD numbers of 3, 6, 14, 28 and 63 would be 2, 3, 4, 5
and 6 respectively. In general, the arrangement of a minimum number of N flip-flops can be used to
construct any counter with a modulus given by the equation
2
N − 1 + 1 ≤ modulus ≤ 2
N
(11.1)
11.4 Binary Ripple Counter – Operational Basics
The operation of a binary ripple counter can be best explained with the help of a typical counter of
this type. Figure 11.2(a) shows a four-bit ripple counter implemented with negative edge-triggered
J-K flip-flops wired as toggle flip-flops. The output of the first flip-flop feeds the clock input of the
second, and the output of the second flip-flop feeds the clock input of the third, the output of which
in turn feeds the clock input of the fourth flip-flop. The outputs of the four flip-flops are designated as
Q 0 (LSB flip-flop), Q 1 , Q 2 and Q 3 (MSB flip-flop). Figure 11.2(b) shows the waveforms appearing at
Q 0 , Q 1 , Q 2 and Q 3 outputs as the clock signal goes through successive cycles of trigger pulses. The
counter functions as follows.
Let us assume that all the flip-flops are initially cleared to the ‘0’ state. On HIGH-to-LOW transition
of the first clock pulse, Q 0 goes from ‘0’ to ‘1’ owing to the toggling action. As the flip-flops used
are negative edge-triggered ones, the ‘0’ to ‘1’ transition of Q 0 does not trigger flip-flop FF1. FF1,
along with FF2 and FF3, remains in its ‘0’ state. So, on the occurrence of the first negative-going
clock transition, Q 0 = 1, Q 1 = 0, Q 2 = 0 and Q 3 = 0.
On the HIGH-to-LOW transition of the second clock pulse, Q 0 toggles again. That is, it goes from
‘1’ to ‘0’. This ‘1’ to ‘0’ transition at the Q 0 output triggers FF1, the output Q 1 of which goes from ‘0’
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ripple counter from this logic family can not be clocked faster than 10 MHz. The upper limit on the
clock frequency further decreases with increase in the number of bits to be handled by the counter.
11.2 Synchronous Counter
In a synchronous counter, also known as a parallel counter, all the flip-flops in the counter change
state at the same time in synchronism with the input clock signal. The clock signal in this case is
simultaneously applied to the clock inputs of all the flip-flops. The delay involved in this case is equal
to the propagation delay of one flip-flop only, irrespective of the number of flip-flops used to construct
the counter. In other words, the delay is independent of the size of the counter.
11.3 Modulus of a Counter
The modulus (MOD number) of a counter is the number of different logic states it goes through before
it comes back to the initial state to repeat the count sequence. An n-bit counter that counts through
all its natural states and does not skip any of the states has a modulus of 2
n . We can see that such
counters have a modulus that is an integral power of 2, that is, 2, 4, 8, 16 and so on. These can be
modified with the help of additional combinational logic to get a modulus of less than 2
n .
To determine the number of flip-flops required to build a counter having a given modulus, identify
the smallest integer m that is either equal to or greater than the desired modulus and is also equal
to an integral power of 2. For instance, if the desired modulus is 10, which is the case in a decade
counter, the smallest integer greater than or equal to 10 and which is also an integral power of 2 is
16. The number of flip-flops in this case would be 4, as 16 = 2
4 . On the same lines, the number of
flip-flops required to construct counters with MOD numbers of 3, 6, 14, 28 and 63 would be 2, 3, 4, 5
and 6 respectively. In general, the arrangement of a minimum number of N flip-flops can be used to
construct any counter with a modulus given by the equation
2
N − 1 + 1 ≤ modulus ≤ 2
N
(11.1)
11.4 Binary Ripple Counter – Operational Basics
The operation of a binary ripple counter can be best explained with the help of a typical counter of
this type. Figure 11.2(a) shows a four-bit ripple counter implemented with negative edge-triggered
J-K flip-flops wired as toggle flip-flops. The output of the first flip-flop feeds the clock input of the
second, and the output of the second flip-flop feeds the clock input of the third, the output of which
in turn feeds the clock input of the fourth flip-flop. The outputs of the four flip-flops are designated as
Q 0 (LSB flip-flop), Q 1 , Q 2 and Q 3 (MSB flip-flop). Figure 11.2(b) shows the waveforms appearing at
Q 0 , Q 1 , Q 2 and Q 3 outputs as the clock signal goes through successive cycles of trigger pulses. The
counter functions as follows.
Let us assume that all the flip-flops are initially cleared to the ‘0’ state. On HIGH-to-LOW transition
of the first clock pulse, Q 0 goes from ‘0’ to ‘1’ owing to the toggling action. As the flip-flops used
are negative edge-triggered ones, the ‘0’ to ‘1’ transition of Q 0 does not trigger flip-flop FF1. FF1,
along with FF2 and FF3, remains in its ‘0’ state. So, on the occurrence of the first negative-going
clock transition, Q 0 = 1, Q 1 = 0, Q 2 = 0 and Q 3 = 0.
On the HIGH-to-LOW transition of the second clock pulse, Q 0 toggles again. That is, it goes from
‘1’ to ‘0’. This ‘1’ to ‘0’ transition at the Q 0 output triggers FF1, the output Q 1 of which goes from ‘0’