380
Digital Electronics
S
Q
R
FF
Clk
(c)
Q
Figure 10.21 (continued).
(a)
R
0
0
1
1
0
0
1
1
Q n+1
Q n
Q n
Q n
Q n
Q n
Invalid
1
0
S
0
0
0
0
1
1
1
1
Clk
0
1
0
1
0
1
0
1
(b)
S
Q
Q
–
R
2
1
Clk
Figure 10.22 Clocked R-S flip-flop with active LOW inputs.