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Digital Electronics
that, when one of the transistors was in saturation, the other was in cut-off. This implies that, if we had
taken outputs from the collectors of both transistors, then the two outputs would be complementary.
In the flip-flops of various types that are available in IC form, we will see that all these devices offer
complementary outputs usually designated as Q and QQ
The R-S flip-flop is the most basic of all flip-flops. The letters ‘R’ and ‘S’ here stand for RESET
and SET. When the flip-flop is SET, its Q output goes to a ‘1’ state, and when it is RESET it goes to
a ‘0’ state. The Q output is the complement of the Q output at all times.
10.3.1 R-S Flip-Flop with Active LOW Inputs
Figure 10.17(a) shows a NAND gate implementation of an R-S flip-flop with active LOW inputs. The
two NAND gates are cross-coupled. That is, the output of NAND 1 is fed back to one of the inputs
of NAND 2, and the output of NAND 2 is fed back to one of the inputs of NAND 1. The remaining
inputs of NAND 1 and NAND 2 are the S and R inputs. The outputs of NAND 1 and NAND 2 are
respectively Q and Q outputs.
The fact that this configuration follows the function table of Fig. 10.17(c) can be explained. We will
look at different entries of the function table, one at a time.
Let us take the case of R = S = 1 (the first entry in the function table). We will prove that, for
R = S = 1, the Q output remains in its existing state. In the truth table, Q n represents the existing state
and Q n+1 represents the state of the flip-flop after it has been triggered by an appropriate pulse at the
R or S input. Let us assume that Q = 0 initially. This ‘0’ state fed back to one of the inputs of gate 2
ensures that Q = 1. The ‘1’ state of Q fed back to one of the inputs of gate 1 along with S = 1 ensures
that Q = 0. Thus, R = S = 1 holds the existing stage. Now, if Q was initially in the ‘1’ state and not
the ‘0’ state, this ‘1’ fed back to one of the inputs of gate 2 along with R = 1 forces Q to be in the ‘0’
state. The ‘0’ state, when fed back to one of the inputs of gate 1, ensures that Q remains in its existing
state of logic ‘1’. Thus, whatever the state of Q, R = S = 1 holds the existing state.
Let us now look at the second entry of the function table where S = 0 and R = 1. We can see that
such an input combination forces the Q output to the ‘1’ state. On similar lines, the input combination
S = 1 and R = 0 (third entry of the truth table) forces the Q output to the ‘0’ state. It would be
interesting to analyse what happens when S = R = 0. This implies that both Q and Q outputs should
go to the ‘1’ state, as one of the inputs of a NAND gate being a logic ‘0’ should force its output to the
logic ‘1’ state irrespective of the status of the other input. This is an undesired state as Q and Q outputs
are to be the complement of each other. The input condition (i.e. R = S = 0) that causes such a situation
is therefore considered to be an invalid condition and is forbidden. Figure 10.17(b) shows the logic
symbol of such a flip-flop. The R and S inputs here have been shown as active LOW inputs, which is
obvious as this flip-flop of Fig. 10.17(a) is SET (that is, Q = 1) when S = 0 and RESET (that is, Q = 0)
when R = 0. Thus, R and S are active when LOW. The term CLEAR input is also used sometimes in
place of RESET. The operation of the R-S flip-flop of Fig. 10.17(a) can be summarized as follows:
1. SET = RESET = 1 is the normal resting condition of the flip-flop. It has no effect on the output state of
the flip-flop. Both Q and Q outputs remain in the logic state they were in prior to this input condition.
2. SET = 0 and RESET = 1 sets the flip-flop. Q and Q respectively go to the ‘1’ and ‘0’ state.
3. SET = 1 and RESET = 0 resets or clears the flip-flop. Q and Q respectively go to the ‘0’ and ‘1’ state.
4. SET = RESET = 0 is forbidden as such a condition tries to set (that is, Q = 1 ) and reset (that
is, Q = 1) the flip-flop at the same time. To be more precise, SET and RESET inputs in the R-S
flip-flop cannot be active at the same time.
The R-S flip-flop of Fig. 10.17(a) is also referred to as an R-S latch. This is because any combination
at the inputs immediately manifests itself at the output as per the truth table.
Digital Electronics
that, when one of the transistors was in saturation, the other was in cut-off. This implies that, if we had
taken outputs from the collectors of both transistors, then the two outputs would be complementary.
In the flip-flops of various types that are available in IC form, we will see that all these devices offer
complementary outputs usually designated as Q and QQ
The R-S flip-flop is the most basic of all flip-flops. The letters ‘R’ and ‘S’ here stand for RESET
and SET. When the flip-flop is SET, its Q output goes to a ‘1’ state, and when it is RESET it goes to
a ‘0’ state. The Q output is the complement of the Q output at all times.
10.3.1 R-S Flip-Flop with Active LOW Inputs
Figure 10.17(a) shows a NAND gate implementation of an R-S flip-flop with active LOW inputs. The
two NAND gates are cross-coupled. That is, the output of NAND 1 is fed back to one of the inputs
of NAND 2, and the output of NAND 2 is fed back to one of the inputs of NAND 1. The remaining
inputs of NAND 1 and NAND 2 are the S and R inputs. The outputs of NAND 1 and NAND 2 are
respectively Q and Q outputs.
The fact that this configuration follows the function table of Fig. 10.17(c) can be explained. We will
look at different entries of the function table, one at a time.
Let us take the case of R = S = 1 (the first entry in the function table). We will prove that, for
R = S = 1, the Q output remains in its existing state. In the truth table, Q n represents the existing state
and Q n+1 represents the state of the flip-flop after it has been triggered by an appropriate pulse at the
R or S input. Let us assume that Q = 0 initially. This ‘0’ state fed back to one of the inputs of gate 2
ensures that Q = 1. The ‘1’ state of Q fed back to one of the inputs of gate 1 along with S = 1 ensures
that Q = 0. Thus, R = S = 1 holds the existing stage. Now, if Q was initially in the ‘1’ state and not
the ‘0’ state, this ‘1’ fed back to one of the inputs of gate 2 along with R = 1 forces Q to be in the ‘0’
state. The ‘0’ state, when fed back to one of the inputs of gate 1, ensures that Q remains in its existing
state of logic ‘1’. Thus, whatever the state of Q, R = S = 1 holds the existing state.
Let us now look at the second entry of the function table where S = 0 and R = 1. We can see that
such an input combination forces the Q output to the ‘1’ state. On similar lines, the input combination
S = 1 and R = 0 (third entry of the truth table) forces the Q output to the ‘0’ state. It would be
interesting to analyse what happens when S = R = 0. This implies that both Q and Q outputs should
go to the ‘1’ state, as one of the inputs of a NAND gate being a logic ‘0’ should force its output to the
logic ‘1’ state irrespective of the status of the other input. This is an undesired state as Q and Q outputs
are to be the complement of each other. The input condition (i.e. R = S = 0) that causes such a situation
is therefore considered to be an invalid condition and is forbidden. Figure 10.17(b) shows the logic
symbol of such a flip-flop. The R and S inputs here have been shown as active LOW inputs, which is
obvious as this flip-flop of Fig. 10.17(a) is SET (that is, Q = 1) when S = 0 and RESET (that is, Q = 0)
when R = 0. Thus, R and S are active when LOW. The term CLEAR input is also used sometimes in
place of RESET. The operation of the R-S flip-flop of Fig. 10.17(a) can be summarized as follows:
1. SET = RESET = 1 is the normal resting condition of the flip-flop. It has no effect on the output state of
the flip-flop. Both Q and Q outputs remain in the logic state they were in prior to this input condition.
2. SET = 0 and RESET = 1 sets the flip-flop. Q and Q respectively go to the ‘1’ and ‘0’ state.
3. SET = 1 and RESET = 0 resets or clears the flip-flop. Q and Q respectively go to the ‘0’ and ‘1’ state.
4. SET = RESET = 0 is forbidden as such a condition tries to set (that is, Q = 1 ) and reset (that
is, Q = 1) the flip-flop at the same time. To be more precise, SET and RESET inputs in the R-S
flip-flop cannot be active at the same time.
The R-S flip-flop of Fig. 10.17(a) is also referred to as an R-S latch. This is because any combination
at the inputs immediately manifests itself at the output as per the truth table.