Programmable Logic Devices
351
I/O Blocks
I/O Blocks
I/O Blocks
I/O Blocks
Routing
Channels
Logic
Block
Rows
(a)
Input
Multiplexer-based
Circuit Block
Output
(b)
Inputs
Figure 9.41 Actel FPGA.
of traditional gate arrays comprising logic blocks arranged in horizontal rows with horizontal routing
channels between adjacent rows, as shown in Fig. 9.41(a). Actel chips also have vertical wires that
overlay the logic blocks to provide signal paths that span multiple rows. These are not shown in Fig.
9.41(a). The logic block is not LUT based. Instead, it comprises an AND gate and an OR gate feeding
a multiplexer circuit block, as shown in Fig. 9.41(b). The multiplexer circuit, along with the two gates,
can realize a large range of logic functions. In the case of Act-3 FPGAs, 50 % of the logic blocks also
contain a flip-flop.