350
Digital Electronics
Table 9.6 Salient features of the XC-4000X and XC-4000E series of FPGAs.
Device
Logic
Maximum
CLB
Number
Number
Maximum
number
cells
logic gates
matrix
of CLBs
of flip-flops
user I/Os
(no RAM)
XC4002XL
152
1 600
8 × 8
64
256
64
XC4003E
238
3 000
10 × 10
100
360
80
XC4005E/XL
466
5 000
14 × 14
196
616
112
XC4006E
608
6 000
16 × 16
256
768
128
XC4008E
770
8 000
18 × 18
324
936
144
XC4010E/XL
950
10 000
20 × 20
400
1120
160
XC4013E/XL
1368
13 000
24 × 24
576
1536
192
XC4020E/XL
1862
20 000
28 × 28
784
2016
224
XC4025E
2432
25 000
32 × 32
1024
2560
256
XC4028EX/
3078
28 000
32 × 32
1024
2560
256
XC4036EX/XL
3078
36 000
36 × 36
1296
3168
288
XC4044XL
3800
44 000
40 × 40
1600
3840
320
XC4052
4598
52 000
44 × 44
1936
4576
352
XC4062XL
5472
62 000
48 × 48
2304
5376
384
XC4085
7448
85 000
56 × 56
3136
7168
448
Table 9.7 Salient features of the FLEX-8000 series of devices.
Device number
Usable Gates
Flip-flops
Logic Array
Blocks
(LAB)
Logic
Elements
(LE)
Maximum User I/O PIns
EPF 8282A/AV
2 500
282
26
208
78
EPF 8452A
4 000
452
42
336
120
EPF 8636A
6 000
636
63
504
136
EPF 8820A
8 000
820
84
672
152
EPF 81188A
12 000
1188
126
1008
184
EPF 81500A
16 000
1500
162
1296
208
configured to serve as an SRAM block with a variable aspect ratio of 256 × 8, 512 × 4, 1K × 2 or
2K × 1.
AT&T offers SRAM-based FPGAs that are similar in architecture to those offered by Xilinx. The
overall structure is called an optimized reconfigurable cell array (ORCA). The basic logic block is
referred to as a programmable function unit (PFU). Similarities with the Xilinx-4000 series FPGAs
include arithmetic circuitry being a part of the PFU and PFU configurability as a RAM. The PFU
can be configured as either four four-input LUTs or as two five-input LUTs or as one six-input LUT.
When configured as four-input LUTs, it is essential that the various LUT inputs come from the same
PFU input. Although on the one hand this reduces the functionality of the PFU, on the other hand it
significantly reduces the associated wiring cost.
Actel FPGAs use antifuse technology. Actel offers three main families of FPGA devices, namely
Act-1, Act-2 and Act-3. All three series of devices have similar features. The structure is similar to that
Digital Electronics
Table 9.6 Salient features of the XC-4000X and XC-4000E series of FPGAs.
Device
Logic
Maximum
CLB
Number
Number
Maximum
number
cells
logic gates
matrix
of CLBs
of flip-flops
user I/Os
(no RAM)
XC4002XL
152
1 600
8 × 8
64
256
64
XC4003E
238
3 000
10 × 10
100
360
80
XC4005E/XL
466
5 000
14 × 14
196
616
112
XC4006E
608
6 000
16 × 16
256
768
128
XC4008E
770
8 000
18 × 18
324
936
144
XC4010E/XL
950
10 000
20 × 20
400
1120
160
XC4013E/XL
1368
13 000
24 × 24
576
1536
192
XC4020E/XL
1862
20 000
28 × 28
784
2016
224
XC4025E
2432
25 000
32 × 32
1024
2560
256
XC4028EX/
3078
28 000
32 × 32
1024
2560
256
XC4036EX/XL
3078
36 000
36 × 36
1296
3168
288
XC4044XL
3800
44 000
40 × 40
1600
3840
320
XC4052
4598
52 000
44 × 44
1936
4576
352
XC4062XL
5472
62 000
48 × 48
2304
5376
384
XC4085
7448
85 000
56 × 56
3136
7168
448
Table 9.7 Salient features of the FLEX-8000 series of devices.
Device number
Usable Gates
Flip-flops
Logic Array
Blocks
(LAB)
Logic
Elements
(LE)
Maximum User I/O PIns
EPF 8282A/AV
2 500
282
26
208
78
EPF 8452A
4 000
452
42
336
120
EPF 8636A
6 000
636
63
504
136
EPF 8820A
8 000
820
84
672
152
EPF 81188A
12 000
1188
126
1008
184
EPF 81500A
16 000
1500
162
1296
208
configured to serve as an SRAM block with a variable aspect ratio of 256 × 8, 512 × 4, 1K × 2 or
2K × 1.
AT&T offers SRAM-based FPGAs that are similar in architecture to those offered by Xilinx. The
overall structure is called an optimized reconfigurable cell array (ORCA). The basic logic block is
referred to as a programmable function unit (PFU). Similarities with the Xilinx-4000 series FPGAs
include arithmetic circuitry being a part of the PFU and PFU configurability as a RAM. The PFU
can be configured as either four four-input LUTs or as two five-input LUTs or as one six-input LUT.
When configured as four-input LUTs, it is essential that the various LUT inputs come from the same
PFU input. Although on the one hand this reduces the functionality of the PFU, on the other hand it
significantly reduces the associated wiring cost.
Actel FPGAs use antifuse technology. Actel offers three main families of FPGA devices, namely
Act-1, Act-2 and Act-3. All three series of devices have similar features. The structure is similar to that