Programmable Logic Devices
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VHDL (VHSIC HDL), Verilog and JHDL (Java HDL). VHSIC stands for Very High-Speed Integrated
Circuit.
The second type of software program is a computer program, called a logic compiler, that is used
to transform a source code written in HDL into a bit stream. Logic compilers are available from
manufacturers or third-party vendors. In the paragraphs to follow, we will briefly describe each of the
hardware description languages mentioned above.
9.11.1 ABEL-Hardware Description Language
ABEL-HDL from DATA I/O was intended for relatively simpler PLD circuit designs that could be
implemented on SPLDs. ABEL allows the designers to describe the digital circuit designs expressed
in the form of truth tables, Boolean functions, state diagrams or any combination of these. It also
allows the designer to optimize the design through design validation without specifying a device. In
other words, ABEL-HDL facilitates writing hardware-independent programs, and it is only after the
design verification and optimization have taken place that the PLD device is chosen. The source code
written in the ABEL environment is in standard format to have interface compatibility with other
tools.
9.11.2 VHDL-VHSIC Hardware Description Language
VHDL is the most widely used hardware description language used for the purpose of describing
complex digital circuit designs that would be implemented on CPLDs and FPGAs. VHDL was originally
developed to document the behaviour of ASICs used by various manufacturers in their equipment. It
was subsequently followed by the development of logic simulation and synthesis tools that could read
VHDL files and output a definition of the physical implementation of the circuit. With modern synthesis
tools capable of extracting various digital building blocks such as counters, RAMs, arithmetic blocks,
etc., and implementing them as specified by the user, the same VHDL code could be synthesized
differently for optimum performance.
VHDL is a strongly typed language. One of the key features of VHDL is that it allows the behaviour
of the intended hardware to be described and then verified before the design is translated into actual
hardware with the help of synthesis tools. Another feature of VHDL that makes it attractive for digital
system design is that it allows description of a concurrent system.
9.11.3 Verilog
Verilog, like VHDL, supports design, design validation and subsequent implementation of analogue,
digital and mixed signal circuits at various levels of abstraction. Verilog-based design consists of a
hierarchy of modules whose behaviour is defined by concurrent and sequential statements. Sequential
statements are placed inside a ‘begin/end’ block and sequential statements contained inside the block
are executed sequentially. All concurrent statements and all ‘begin/end’ blocks in the design are
executed in parallel. A subset of statements in Verilog is synthesizable. Therefore, if in a given design
the different modules use only synthesizable statements, the design can be translated into a netlist,
which can further be translated into a bit stream.
Verilog has some similarities and dissimilarities with C-language. It has a similar preprocessor,
similar major control keywords like ‘if’, ‘while’, etc., and also a similar formatting mechanism in the
printing routines and language operators. Dissimilarities include the use of ‘begin/end’ instead of curly
339
VHDL (VHSIC HDL), Verilog and JHDL (Java HDL). VHSIC stands for Very High-Speed Integrated
Circuit.
The second type of software program is a computer program, called a logic compiler, that is used
to transform a source code written in HDL into a bit stream. Logic compilers are available from
manufacturers or third-party vendors. In the paragraphs to follow, we will briefly describe each of the
hardware description languages mentioned above.
9.11.1 ABEL-Hardware Description Language
ABEL-HDL from DATA I/O was intended for relatively simpler PLD circuit designs that could be
implemented on SPLDs. ABEL allows the designers to describe the digital circuit designs expressed
in the form of truth tables, Boolean functions, state diagrams or any combination of these. It also
allows the designer to optimize the design through design validation without specifying a device. In
other words, ABEL-HDL facilitates writing hardware-independent programs, and it is only after the
design verification and optimization have taken place that the PLD device is chosen. The source code
written in the ABEL environment is in standard format to have interface compatibility with other
tools.
9.11.2 VHDL-VHSIC Hardware Description Language
VHDL is the most widely used hardware description language used for the purpose of describing
complex digital circuit designs that would be implemented on CPLDs and FPGAs. VHDL was originally
developed to document the behaviour of ASICs used by various manufacturers in their equipment. It
was subsequently followed by the development of logic simulation and synthesis tools that could read
VHDL files and output a definition of the physical implementation of the circuit. With modern synthesis
tools capable of extracting various digital building blocks such as counters, RAMs, arithmetic blocks,
etc., and implementing them as specified by the user, the same VHDL code could be synthesized
differently for optimum performance.
VHDL is a strongly typed language. One of the key features of VHDL is that it allows the behaviour
of the intended hardware to be described and then verified before the design is translated into actual
hardware with the help of synthesis tools. Another feature of VHDL that makes it attractive for digital
system design is that it allows description of a concurrent system.
9.11.3 Verilog
Verilog, like VHDL, supports design, design validation and subsequent implementation of analogue,
digital and mixed signal circuits at various levels of abstraction. Verilog-based design consists of a
hierarchy of modules whose behaviour is defined by concurrent and sequential statements. Sequential
statements are placed inside a ‘begin/end’ block and sequential statements contained inside the block
are executed sequentially. All concurrent statements and all ‘begin/end’ blocks in the design are
executed in parallel. A subset of statements in Verilog is synthesizable. Therefore, if in a given design
the different modules use only synthesizable statements, the design can be translated into a netlist,
which can further be translated into a bit stream.
Verilog has some similarities and dissimilarities with C-language. It has a similar preprocessor,
similar major control keywords like ‘if’, ‘while’, etc., and also a similar formatting mechanism in the
printing routines and language operators. Dissimilarities include the use of ‘begin/end’ instead of curly