338
Digital Electronics
Design Entry
Simulation
Design Constraints
Place & Route
Download
Design Library
Synthesis
Figure 9.34 Programmable logic design and development process.
The design entry step is either followed by or interspersed with periodic functional simulation. The
simulator executes the design for a given set of inputs and confirms that the logic is functionally correct.
Hardware compilation comes next. It involves two steps. The first step is synthesis, and the result
of that is a hardware representation called a netlist. The netlist is device independent and its contents
do not depend on the parameters of the PLD to be programmed. It is usually stored in a standard
format called the electronic design interchange format (EDIF). The second step, called place and route,
involves mapping of the logical structure described in the netlist onto actual logic blocks, interconnects
and inputs/outputs. The place and route process produces a bit stream, which is nothing but the binary
data that must be loaded into CPLD/FPGA to make the chip execute the intended hardware design. It
may be mentioned here that each device family has its own proprietary bit stream format.
9.11 Programming Languages
During the PLD development cycle, from design entry to the generation of a bit stream that can
be loaded onto the chip using some kind of electronic programming system, two types of software
program are needed to perform two different functions.
The first is a hardware description language (HDL), which is needed at the design entry stage.
HDL is a software programming language that is used to model or describe the intended operation of
a piece of hardware. In the present case, this is the function that the PLD chip is intended to perform
after it is programmed. It may be worth mentioning here that modern computer languages, including
both hardware description languages and high-level programming languages, almost invariably contain
declarative and executable statements, and the hardware description languages are particularly rich
in the former. If we compare the results of a high-level programming language such as C++ and
an HDL, it will be an executable program in the case of the former and declarative in the case
of the latter. Hardware description languages that have evolved over the years include ABEL-HDL,
Digital Electronics
Design Entry
Simulation
Design Constraints
Place & Route
Download
Design Library
Synthesis
Figure 9.34 Programmable logic design and development process.
The design entry step is either followed by or interspersed with periodic functional simulation. The
simulator executes the design for a given set of inputs and confirms that the logic is functionally correct.
Hardware compilation comes next. It involves two steps. The first step is synthesis, and the result
of that is a hardware representation called a netlist. The netlist is device independent and its contents
do not depend on the parameters of the PLD to be programmed. It is usually stored in a standard
format called the electronic design interchange format (EDIF). The second step, called place and route,
involves mapping of the logical structure described in the netlist onto actual logic blocks, interconnects
and inputs/outputs. The place and route process produces a bit stream, which is nothing but the binary
data that must be loaded into CPLD/FPGA to make the chip execute the intended hardware design. It
may be mentioned here that each device family has its own proprietary bit stream format.
9.11 Programming Languages
During the PLD development cycle, from design entry to the generation of a bit stream that can
be loaded onto the chip using some kind of electronic programming system, two types of software
program are needed to perform two different functions.
The first is a hardware description language (HDL), which is needed at the design entry stage.
HDL is a software programming language that is used to model or describe the intended operation of
a piece of hardware. In the present case, this is the function that the PLD chip is intended to perform
after it is programmed. It may be worth mentioning here that modern computer languages, including
both hardware description languages and high-level programming languages, almost invariably contain
declarative and executable statements, and the hardware description languages are particularly rich
in the former. If we compare the results of a high-level programming language such as C++ and
an HDL, it will be an executable program in the case of the former and declarative in the case
of the latter. Hardware description languages that have evolved over the years include ABEL-HDL,