Programmable Logic Devices
331
CPLD architecture particularly suits those designs that exploit wide AND/OR gates and do not require
a large number of flip-flops.
The reprogramming feature of CPLDs makes the incorporation of design changes very easy. With
the availability of CPLDs having an in-circuit programming feature, it is even possible to reconfigure
the hardware without power down. Changing protocol in a communication circuit could be one such
example. One of the most significant advantages of CPLD architecture comes from its simple SPLDlike structure, which allows the design to partition naturally into SPLD-like blocks. This leads to a
much more predictable timing or speed performance than would be possible if the design were split
into many pieces and mapped into different areas of the chip.
9.8 Field-Programmable Gate Arrays
As outlined earlier, it is not practical to increase the logic capacity with a CPLD architecture beyond
a certain point. The highest-capacity general-purpose logic chips available today are the traditional
gate arrays, which comprise an array of prefabricated transistors. The chip can be customized during
fabrication as per the user’s logic design by specifying the metal interconnect pattern. These chips
are also referred to as mask-programmable gate arrays (MPGAs). These, however, are not fieldprogrammable devices. A field-programmable gate array (FPGA) chip is the user-programmable
equivalent of an MPGA chip.
9.8.1 Internal Architecture
An FPGA consists of an array of uncommitted configurable logic blocks, programmable interconnects
and I/O blocks. The basic architecture of an FPGA was shown earlier in Fig. 9.7 when presenting an
overview of programmable logic devices. As outlined earlier, the basic difference between a CPLD
and an FPGA lies in their internal architecture. CPLD architecture is dominated by a relatively smaller
number of programmable sum-of-products logic arrays feeding a small number of clocked flip-flops,
which makes the architecture less flexible but with more predictable timing characteristics. On the
other hand, FPGA architecture is dominated by programmable interconnects, and the configurable logic
blocks are relatively simpler. Logic blocks within an FPGA can be as small as the macrocells in a
PLD, called fine-grained architecture, or larger and more complex, called coarse-grained architecture.
However, they are never as large as the entire PLD like the logic blocks of a CPLD. This feature
makes these devices far more flexible in terms of the range of designs that can be implemented with
these devices.
Contemporary FPGAs have an on-chip presence of higher-level embedded functions and embedded
memories. Some of them even come with an on-chip microprocessor and related peripherals to constitute
what is called a complete ‘system on a programmable chip’. Virtex-II Pro and Virtex-4 FPGA devices
from Xilinx are examples. These devices have one or more PowerPC processors embedded within the
FPGA logic fabric.
Figure 9.27 shows a typical logic block of an FPGA. It consists of a four-input look-up table
(LUT) whose output feeds a clocked flip-flop. The output can either be a registered output or an
unregistered LUT output. Selection of the output takes place in the multiplexer. An LUT is nothing
but a small one-bit wide memory array with its address lines representing the inputs to the logic
block and a one-bit output acting as the LUT output. An LUT with n inputs can realize any logic
function of n inputs by programming the truth table of the desired logic function directly into the
memory.
331
CPLD architecture particularly suits those designs that exploit wide AND/OR gates and do not require
a large number of flip-flops.
The reprogramming feature of CPLDs makes the incorporation of design changes very easy. With
the availability of CPLDs having an in-circuit programming feature, it is even possible to reconfigure
the hardware without power down. Changing protocol in a communication circuit could be one such
example. One of the most significant advantages of CPLD architecture comes from its simple SPLDlike structure, which allows the design to partition naturally into SPLD-like blocks. This leads to a
much more predictable timing or speed performance than would be possible if the design were split
into many pieces and mapped into different areas of the chip.
9.8 Field-Programmable Gate Arrays
As outlined earlier, it is not practical to increase the logic capacity with a CPLD architecture beyond
a certain point. The highest-capacity general-purpose logic chips available today are the traditional
gate arrays, which comprise an array of prefabricated transistors. The chip can be customized during
fabrication as per the user’s logic design by specifying the metal interconnect pattern. These chips
are also referred to as mask-programmable gate arrays (MPGAs). These, however, are not fieldprogrammable devices. A field-programmable gate array (FPGA) chip is the user-programmable
equivalent of an MPGA chip.
9.8.1 Internal Architecture
An FPGA consists of an array of uncommitted configurable logic blocks, programmable interconnects
and I/O blocks. The basic architecture of an FPGA was shown earlier in Fig. 9.7 when presenting an
overview of programmable logic devices. As outlined earlier, the basic difference between a CPLD
and an FPGA lies in their internal architecture. CPLD architecture is dominated by a relatively smaller
number of programmable sum-of-products logic arrays feeding a small number of clocked flip-flops,
which makes the architecture less flexible but with more predictable timing characteristics. On the
other hand, FPGA architecture is dominated by programmable interconnects, and the configurable logic
blocks are relatively simpler. Logic blocks within an FPGA can be as small as the macrocells in a
PLD, called fine-grained architecture, or larger and more complex, called coarse-grained architecture.
However, they are never as large as the entire PLD like the logic blocks of a CPLD. This feature
makes these devices far more flexible in terms of the range of designs that can be implemented with
these devices.
Contemporary FPGAs have an on-chip presence of higher-level embedded functions and embedded
memories. Some of them even come with an on-chip microprocessor and related peripherals to constitute
what is called a complete ‘system on a programmable chip’. Virtex-II Pro and Virtex-4 FPGA devices
from Xilinx are examples. These devices have one or more PowerPC processors embedded within the
FPGA logic fabric.
Figure 9.27 shows a typical logic block of an FPGA. It consists of a four-input look-up table
(LUT) whose output feeds a clocked flip-flop. The output can either be a registered output or an
unregistered LUT output. Selection of the output takes place in the multiplexer. An LUT is nothing
but a small one-bit wide memory array with its address lines representing the inputs to the logic
block and a one-bit output acting as the LUT output. An LUT with n inputs can realize any logic
function of n inputs by programming the truth table of the desired logic function directly into the
memory.