330
Digital Electronics
Inputs
Global
Set/Reset
Global
Clock
Additional
Product
Terms
(from other
Macrocells)
Product Term Set
0
1
Product Term Clock
Product Term Reset
D/T
S
Q
R
To
Switch
Matrix
To
I/O
Blocks
Product
Term
Allocator
Product Term OE
SR
FF
Figure 9.26 Macrocell architecture.
additional product terms from other macrocells in the same logic block, apart from a maximum of five
product terms from within the same macrocell.
Figure 9.26 shows the logic diagram of a macrocell typical of macrocells in the logic blocks of most
contemporary CPLDs. The diagram is self-explanatory. There may be minor variations in devices from
different manufacturers. For example, macrocells in the XC-7000 series CPLDs from Xilinx have two
OR gates fed from a two-bit arithmetic logic unit (ALU) and its output feeds a configurable flip-flop.
9.7.2 Applications
Owing to their less flexible internal architecture leading to predictable timing performance, high speed
and a range of logic capacities, CPLDs find extensive use in a wide assortment of applications. These
include the implementation of random glue logic in prototyping small gate arrays, implementing critical
control designs such as graphics controllers, cache control, UARTs, LAN controllers and many more.
CPLDs are fast replacing SPLDs in complex designs. Complex designs using a large number of
SPLDs can be replaced with a CPLD-based design with a much smaller number of devices. This
is particularly attractive in portable applications such as mobile phones, digital assistants and so on.