328
Digital Electronics
Figures 9.23(a) and (b) respectively show the block schematic representation of a GAL device
and the architecture of a typical OLMC used with GAL devices. The OLMC of the type shown in
Fig. 9.23(b) can be configured to produce four different outputs depending upon the selection inputs.
These include the following:
1. S 1 S 0 = 00: registered mode with active LOW output.
2. S 1 S 0 = 01: registered mode with active HIGH output.
3. S 1 S 0 = 10: combinational mode with active LOW output.
4. S 1 S 0 = 11: combinational mode with active HIGH output.
We can see that two of the four inputs to the 4-to-1 multiplexer are combinational outputs, and the
other two are the registered outputs. Also, of the two combinational outputs, one is an active HIGH
output while the other is an active LOW output. The same is the case with registered outputs. Of the
four inputs to the multiplexer, the one appearing at the output depends upon selection inputs. The 2-to-1
multiplexer ensures that the final output is also available as feedback to the programmable AND array.
9.7 Complex Programmable Logic Devices
If we examine the internal architecture of simple programmable logic devices (SPLDs) such as PLAs
and PALs, we find that it is not practical to increase their complexity beyond a certain level. This
is because the size of the programmable plane (such as the programmable AND plane in a PLA or
PAL device) increases too rapidly with increase in the number of inputs to make it a practically viable
device. One way to increase the logic capacity of simple programmable logic devices is to integrate
multiple SPLDs on a single chip with a programmable interconnect between them. These devices
have the same basic internal structure that we see in the case of SPLDs and are grouped together
in the category of complex programmable logic devices (CPLDs). Typically, CPLDs may offer a
logic capacity equivalent to that of about 50 SPLDs. Programmable logic devices with much higher
logic capacities would require a different approach rather than simple extension of the concept of
SPLDs.
9.7.1 Internal Architecture
As outlined in the previous paragraph, a CPLD is nothing but the integration of multiple PLDs, a
programmable interconnect matrix and an I/O control block on a single chip. Each of the identical
PLDs is referred to as a logic block or function block. Figure 9.24 shows the architecture of a typical
CPLD. As is evident from the block schematic arrangement, the programmable interconnect matrix is
capable of connecting the input or output of any of the logic blocks to any other logic block. Also,
input and output pins connect directly to both the interconnect matrix as well as logic blocks.
Logic blocks may further comprise smaller logic units called macrocells, where each of the macrocells
is a subset of a PLD-like logic block. Figure 9.25 shows the structure of a logic block along with
its interconnections with the programmable interconnect matrix and I/O block. The horizontal greycoloured bars inside the logic block constitute an array of macrocells. Typically, each macrocell
comprises a set of product terms generated by a subset of the programmable AND array and feeding
a configurable output logic. The output logic typically comprises an OR gate, an EX-OR gate and a
flip-flop. The flip-flop in the case of most contemporary CPLDs is configurable as a D-type, J-K, T ,
or R-S flip-flop or can even be transparent. Also, the OR gate can be fed with any or all of the product
terms generated within the macrocell. Most contemporary CPLDs also offer an architecture where the
Digital Electronics
Figures 9.23(a) and (b) respectively show the block schematic representation of a GAL device
and the architecture of a typical OLMC used with GAL devices. The OLMC of the type shown in
Fig. 9.23(b) can be configured to produce four different outputs depending upon the selection inputs.
These include the following:
1. S 1 S 0 = 00: registered mode with active LOW output.
2. S 1 S 0 = 01: registered mode with active HIGH output.
3. S 1 S 0 = 10: combinational mode with active LOW output.
4. S 1 S 0 = 11: combinational mode with active HIGH output.
We can see that two of the four inputs to the 4-to-1 multiplexer are combinational outputs, and the
other two are the registered outputs. Also, of the two combinational outputs, one is an active HIGH
output while the other is an active LOW output. The same is the case with registered outputs. Of the
four inputs to the multiplexer, the one appearing at the output depends upon selection inputs. The 2-to-1
multiplexer ensures that the final output is also available as feedback to the programmable AND array.
9.7 Complex Programmable Logic Devices
If we examine the internal architecture of simple programmable logic devices (SPLDs) such as PLAs
and PALs, we find that it is not practical to increase their complexity beyond a certain level. This
is because the size of the programmable plane (such as the programmable AND plane in a PLA or
PAL device) increases too rapidly with increase in the number of inputs to make it a practically viable
device. One way to increase the logic capacity of simple programmable logic devices is to integrate
multiple SPLDs on a single chip with a programmable interconnect between them. These devices
have the same basic internal structure that we see in the case of SPLDs and are grouped together
in the category of complex programmable logic devices (CPLDs). Typically, CPLDs may offer a
logic capacity equivalent to that of about 50 SPLDs. Programmable logic devices with much higher
logic capacities would require a different approach rather than simple extension of the concept of
SPLDs.
9.7.1 Internal Architecture
As outlined in the previous paragraph, a CPLD is nothing but the integration of multiple PLDs, a
programmable interconnect matrix and an I/O control block on a single chip. Each of the identical
PLDs is referred to as a logic block or function block. Figure 9.24 shows the architecture of a typical
CPLD. As is evident from the block schematic arrangement, the programmable interconnect matrix is
capable of connecting the input or output of any of the logic blocks to any other logic block. Also,
input and output pins connect directly to both the interconnect matrix as well as logic blocks.
Logic blocks may further comprise smaller logic units called macrocells, where each of the macrocells
is a subset of a PLD-like logic block. Figure 9.25 shows the structure of a logic block along with
its interconnections with the programmable interconnect matrix and I/O block. The horizontal greycoloured bars inside the logic block constitute an array of macrocells. Typically, each macrocell
comprises a set of product terms generated by a subset of the programmable AND array and feeding
a configurable output logic. The output logic typically comprises an OR gate, an EX-OR gate and a
flip-flop. The flip-flop in the case of most contemporary CPLDs is configurable as a D-type, J-K, T ,
or R-S flip-flop or can even be transparent. Also, the OR gate can be fed with any or all of the product
terms generated within the macrocell. Most contemporary CPLDs also offer an architecture where the