312
Digital Electronics
Solution
(a) The number of inputs required here would be eight. The result of multiplication would be in eight
bits. Therefore, the size of the PROM = 2
8
× 8 = 256 × 8.
(b) The number of inputs = 8 + 8 + 3 = 19 (the number of selection inputs = 3). The number of outputs
= 2. Therefore, the size of the PROM = 2
19
× 2 = 512K × 2.
(c) The number of inputs = 4 (augend bits) + 4 (addend bits) + 1 (carry-in) + 1 (control input) = 10.
The number of outputs = 4 (sum or subtraction output bits) + 1 (carry or borrow bit) = 5. The size
of the PROM = 2
10
× 5 = 1024 × 5 = 1K × 5.
9.4 Programmable Logic Array
A programmable logic array (PLA) enables logic functions expressed in sum-of-products form to be
implemented directly. It is similar in concept to a PROM. However, unlike a PROM, the PLA does
not provide full decoding of the input variables and does not generate all possible minterms. While a
PROM has a fixed AND gate array at the input and a programmable OR gate array at the output, a
PLA device has a programmable AND gate array at the input and a programmable OR gate array at the
output. In a PLA device, each of the product terms of the given Boolean function is generated by an
AND gate which can be programmed to form the AND of any subset of inputs or their complements.
The product terms so produced can be summed up in an array of programmable OR gates. Thus, we
have a programmable OR gate array at the output. The input and output gates are constructed in the
form of arrays with input lines orthogonal to product lines and product lines orthogonal to output
lines.
Figure 9.11 shows the internal architecture of a PLA device with four input lines, eight product
lines and four output lines. That is, the programmable AND gate array has eight AND gates. Each
of the AND gates here has eight inputs, corresponding to four input variables and their complements.
The input to each of the AND gates can be programmed to be any of the possible 16 combinations of
four input variables and their complements. Four OR gates at the output can generate four different
Boolean functions, each having a maximum of eight minterms out of 16 minterms possible with four
variables. The logic diagram depicts the unprogrammed state of the device. The internal architecture
shown in Fig. 9.11 can also be represented by the schematic form of Fig. 9.12. PLAs usually have
inverters at the output of OR gates to enable them to implement a given Boolean function in either
AND-OR or AND-OR-INVERT form.
Figure 9.13 shows a generalized block schematic representation of a PLA device having n inputs, m
outputs and k product terms, with n, m and k respectively representing the number of input variables,
the number of OR gates and the number of AND gates. The number of inputs to each OR gate and
each AND gate are k and 2n respectively.
A PLA is specified in terms of the number of inputs, the number of product terms and the number
of outputs. As is clear from the description given in the preceding paragraph, the PLA would have a
total of 2Kn + Km programmable interconnections. A ROM with the same number of input and output
lines would have 2
n
× m programmable interconnections.
A PLA could be either mask programmable or field programmable. In the case of a maskprogrammable PLA, the customer submits a program table to the manufacturer to produce a custommade PLA having the desired internal paths between inputs and outputs. A field-programmable logic
array (FPLA) is programmed by the users themselves by means of a hardware programmer unit
available commercially.
Digital Electronics
Solution
(a) The number of inputs required here would be eight. The result of multiplication would be in eight
bits. Therefore, the size of the PROM = 2
8
× 8 = 256 × 8.
(b) The number of inputs = 8 + 8 + 3 = 19 (the number of selection inputs = 3). The number of outputs
= 2. Therefore, the size of the PROM = 2
19
× 2 = 512K × 2.
(c) The number of inputs = 4 (augend bits) + 4 (addend bits) + 1 (carry-in) + 1 (control input) = 10.
The number of outputs = 4 (sum or subtraction output bits) + 1 (carry or borrow bit) = 5. The size
of the PROM = 2
10
× 5 = 1024 × 5 = 1K × 5.
9.4 Programmable Logic Array
A programmable logic array (PLA) enables logic functions expressed in sum-of-products form to be
implemented directly. It is similar in concept to a PROM. However, unlike a PROM, the PLA does
not provide full decoding of the input variables and does not generate all possible minterms. While a
PROM has a fixed AND gate array at the input and a programmable OR gate array at the output, a
PLA device has a programmable AND gate array at the input and a programmable OR gate array at the
output. In a PLA device, each of the product terms of the given Boolean function is generated by an
AND gate which can be programmed to form the AND of any subset of inputs or their complements.
The product terms so produced can be summed up in an array of programmable OR gates. Thus, we
have a programmable OR gate array at the output. The input and output gates are constructed in the
form of arrays with input lines orthogonal to product lines and product lines orthogonal to output
lines.
Figure 9.11 shows the internal architecture of a PLA device with four input lines, eight product
lines and four output lines. That is, the programmable AND gate array has eight AND gates. Each
of the AND gates here has eight inputs, corresponding to four input variables and their complements.
The input to each of the AND gates can be programmed to be any of the possible 16 combinations of
four input variables and their complements. Four OR gates at the output can generate four different
Boolean functions, each having a maximum of eight minterms out of 16 minterms possible with four
variables. The logic diagram depicts the unprogrammed state of the device. The internal architecture
shown in Fig. 9.11 can also be represented by the schematic form of Fig. 9.12. PLAs usually have
inverters at the output of OR gates to enable them to implement a given Boolean function in either
AND-OR or AND-OR-INVERT form.
Figure 9.13 shows a generalized block schematic representation of a PLA device having n inputs, m
outputs and k product terms, with n, m and k respectively representing the number of input variables,
the number of OR gates and the number of AND gates. The number of inputs to each OR gate and
each AND gate are k and 2n respectively.
A PLA is specified in terms of the number of inputs, the number of product terms and the number
of outputs. As is clear from the description given in the preceding paragraph, the PLA would have a
total of 2Kn + Km programmable interconnections. A ROM with the same number of input and output
lines would have 2
n
× m programmable interconnections.
A PLA could be either mask programmable or field programmable. In the case of a maskprogrammable PLA, the customer submits a program table to the manufacturer to produce a custommade PLA having the desired internal paths between inputs and outputs. A field-programmable logic
array (FPLA) is programmed by the users themselves by means of a hardware programmer unit
available commercially.