Multiplexers and Demultiplexers
289
Table 8.11 Example 8.6.
A
B
C
S
C o
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
3-to-8
Decoder
2
2
2
1
2
0
S
C o
0
1
2
3
4
5
6
7
A
B
C
Figure 8.22 Example 8.6.
Example 8.7
A combinational circuit is defined by F = 0, 2, 5, 6, 7. Hardware implement the Boolean function F
with a suitable decoder and an external OR/NOR gate having the minimum number of inputs.
Solution
The given Boolean function has five three-variable minterms. This implies that the function can be
implemented with a 3-to-8 line decoder and a five-input OR gate. Also, F will have only three
three-variable minterms, which means that F could also be implemented by considering minterms
corresponding to the complement function and using a three-input NOR gate at the output. The second
option uses a NOR gate with fewer inputs and therefore is used instead. F = 0, 2, 5, 6, 7. Therefore,
F = 1, 3, 4.
Figure 8.23 shows the hardware implementation of Boolean function F .