Arithmetic Circuits
239
1
1
1
1
C in
C in
C in
A B
AB
A B
(a)
A B
A B
1
1
C in
C in
C in
A B
AB
A B
(b)
A B
A B
1
1
Figure 7.8 Karnaugh maps for the sum and carry-out of a full adder.
C out = AAB + C in AAB + AABB
(7.11)
Boolean expression (7.10) can be implemented with a two-input EX-OR gate provided that one of
the inputs is C in and the other input is the output of another two-input EX-OR gate with A and B
as its inputs. Similarly, Boolean expression (7.11) can be implemented by ORing two minterms. One
of them is the AND output of A and B. The other is also the output of an AND gate whose inputs
are C in and the output of an EX-OR operation on A and B. The whole idea of writing the Boolean
expressions in this modified form was to demonstrate the use of a half-adder circuit in building a full
adder. Figure 7.10(a) shows logic implementation of Equations (7.10) and (7.11). Figure 7.10(b) is
nothing but Fig. 7.10(a) redrawn with the portion of the circuit representing a half-adder replaced with a
block.
The full adder of the type described above forms the basic building block of binary adders. However,
a single full adder circuit can be used to add one-bit binary numbers only. A cascade arrangement of
these adders can be used to construct adders capable of adding binary numbers with a larger number
of bits. For example, a four-bit binary adder would require four full adders of the type shown in Fig.
7.10 to be connected in cascade. Figure 7.11 shows such an arrangement. (A 3 A 2 A 1 A 0 and (B 3 B 2 B 1 B 0
are the two binary numbers to be added, with A 0 and B 0 representing LSBs and A 3 and B 3 representing
MSBs of the two numbers.
239
1
1
1
1
C in
C in
C in
A B
AB
A B
(a)
A B
A B
1
1
C in
C in
C in
A B
AB
A B
(b)
A B
A B
1
1
Figure 7.8 Karnaugh maps for the sum and carry-out of a full adder.
C out = AAB + C in AAB + AABB
(7.11)
Boolean expression (7.10) can be implemented with a two-input EX-OR gate provided that one of
the inputs is C in and the other input is the output of another two-input EX-OR gate with A and B
as its inputs. Similarly, Boolean expression (7.11) can be implemented by ORing two minterms. One
of them is the AND output of A and B. The other is also the output of an AND gate whose inputs
are C in and the output of an EX-OR operation on A and B. The whole idea of writing the Boolean
expressions in this modified form was to demonstrate the use of a half-adder circuit in building a full
adder. Figure 7.10(a) shows logic implementation of Equations (7.10) and (7.11). Figure 7.10(b) is
nothing but Fig. 7.10(a) redrawn with the portion of the circuit representing a half-adder replaced with a
block.
The full adder of the type described above forms the basic building block of binary adders. However,
a single full adder circuit can be used to add one-bit binary numbers only. A cascade arrangement of
these adders can be used to construct adders capable of adding binary numbers with a larger number
of bits. For example, a four-bit binary adder would require four full adders of the type shown in Fig.
7.10 to be connected in cascade. Figure 7.11 shows such an arrangement. (A 3 A 2 A 1 A 0 and (B 3 B 2 B 1 B 0
are the two binary numbers to be added, with A 0 and B 0 representing LSBs and A 3 and B 3 representing
MSBs of the two numbers.