Logic Families
175
Q 1
Q 2
+VDD
Y=A
–
A
(a)
Q 3
Q 1
+VDD
Y=(A+B)
——
A
(b)
B
Q 2
(c)
Q 3
+VDD
Q 2
Q 1
Y=A.B
B
A
Figure 5.58 (a) NMOS logic circuit inverter, (b) NMOS logic two-input NOR and (c) NMOS logic two-input
NAND.