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Digital Electronics
the conducting Q 1 . When the input is at −V DD or near −V DD , Q 2 conducts and the output goes to
near-zero potential (i.e. logic ‘1’).
Figure 5.57(b) shows a PMOS logic based two-input NOR gate. In the logic arrangement of
Fig. 5.57(b), the output goes to logic ‘1’ state (i.e. ground potential) only when both Q 1 and Q 2 are
conducting. This is possible only when both the inputs are in logic ‘0’ state. For all other possible
input combinations, the output is in logic ‘0’ state, because, with either Q 1 or Q 2 nonconducting, the
output is nearly −V DD through the conducting Q 3 . The circuit of Fig. 5.57(b) thus behaves like a
two-input NOR gate in positive logic. It may be mentioned here that the MOSFET being used as load
[Q 1 in Fig. 5.57(a) and Q 3 in Fig. 5.57(b)] is designed so as to have an ON-resistance that is much
greater than the total ON-resistance of the MOSFETs being used as switches [Q 2 in Fig. 5.57(a) and
Q 1 and Q 2 in Fig. 5.57(b)].
5.7.2 NMOS Logic
The NMOS logic family uses N-channel MOSFETS. N-channel MOS devices require a smaller chip
area per transistor compared with P-channel devices, with the result that NMOS logic offers a higher
density. Also, owing to the greater mobility of the charge carriers in N-channel devices, the NMOS
logic family offers higher speed too. It is for this reason that most of the MOS memory devices and
microprocessors employ NMOS logic or some variation of it such as VMOS, DMOS and HMOS.
VMOS, DMOS and HMOS are only structural variations of NMOS, aimed at further reducing the
propagation delay. Figures 5.58(a), (b) and (c) respectively show an inverter, a two-input NOR and a
two-input NAND using NMOS logic. The logic circuits are self-explanatory.
5.8 Integrated Injection Logic (I
2 L) Family
Integrated injection logic (I
2 L), also known as current injection logic, is well suited to implementing
LSI and VLSI digital functions and is a close competitor to the NMOS logic family. Figure 5.59
shows the basic I
2 L family building block, which is a multicollector bipolar transistor with a current
source driving its base. Transistors Q 3 and Q 4 constitute current sources. The magnitude of current
depends upon externally connected R and applied +V . This current is also known as the injection
current, which gives it its name of injection logic. If input A is HIGH, the injection current through
Q 3 flows through the base-emitter junction of Q 1 . Transistor Q 1 saturates and its collector drops to
a low voltage, typically 50–100 mV. When A is LOW, the injection current is swept away from the
base-emitter junction of Q 1 . Transistor Q 1 becomes open and the injection current through Q 4 saturates
Q 2 , with the result that the Q 1 collector potential equals the base-emitter saturation voltage of Q 2 ,
typically 0.7 V.
The speed of I
2 L family devices is a function of the injection current I and improves with increase in
current, as a higher current allows a faster charging of capacitive loads present at bases of transistors.
The programmable injection current feature is made use of in the I
2 L family of digital ICs to choose
the desired speed depending upon intended application. The logic ‘0’ level is V CE (sat.) of the driving
transistor (Q 1 in the present case), and the logic ‘1’ level is V BE (sat.) of the driven transistor (Q 2
in the present case). Typically, the logic ‘0’ and logic ‘1’ levels are 0.1 and 0.7 V respectively. The
speed–power product of the I
2 L family is typically under 1 pJ.
Multiple collectors of different transistors can be connected together to form wired logic. Figure 5.60
shows one such arrangement, depicting the generation of OR and NOR outputs of two logic variables
A and B.
Digital Electronics
the conducting Q 1 . When the input is at −V DD or near −V DD , Q 2 conducts and the output goes to
near-zero potential (i.e. logic ‘1’).
Figure 5.57(b) shows a PMOS logic based two-input NOR gate. In the logic arrangement of
Fig. 5.57(b), the output goes to logic ‘1’ state (i.e. ground potential) only when both Q 1 and Q 2 are
conducting. This is possible only when both the inputs are in logic ‘0’ state. For all other possible
input combinations, the output is in logic ‘0’ state, because, with either Q 1 or Q 2 nonconducting, the
output is nearly −V DD through the conducting Q 3 . The circuit of Fig. 5.57(b) thus behaves like a
two-input NOR gate in positive logic. It may be mentioned here that the MOSFET being used as load
[Q 1 in Fig. 5.57(a) and Q 3 in Fig. 5.57(b)] is designed so as to have an ON-resistance that is much
greater than the total ON-resistance of the MOSFETs being used as switches [Q 2 in Fig. 5.57(a) and
Q 1 and Q 2 in Fig. 5.57(b)].
5.7.2 NMOS Logic
The NMOS logic family uses N-channel MOSFETS. N-channel MOS devices require a smaller chip
area per transistor compared with P-channel devices, with the result that NMOS logic offers a higher
density. Also, owing to the greater mobility of the charge carriers in N-channel devices, the NMOS
logic family offers higher speed too. It is for this reason that most of the MOS memory devices and
microprocessors employ NMOS logic or some variation of it such as VMOS, DMOS and HMOS.
VMOS, DMOS and HMOS are only structural variations of NMOS, aimed at further reducing the
propagation delay. Figures 5.58(a), (b) and (c) respectively show an inverter, a two-input NOR and a
two-input NAND using NMOS logic. The logic circuits are self-explanatory.
5.8 Integrated Injection Logic (I
2 L) Family
Integrated injection logic (I
2 L), also known as current injection logic, is well suited to implementing
LSI and VLSI digital functions and is a close competitor to the NMOS logic family. Figure 5.59
shows the basic I
2 L family building block, which is a multicollector bipolar transistor with a current
source driving its base. Transistors Q 3 and Q 4 constitute current sources. The magnitude of current
depends upon externally connected R and applied +V . This current is also known as the injection
current, which gives it its name of injection logic. If input A is HIGH, the injection current through
Q 3 flows through the base-emitter junction of Q 1 . Transistor Q 1 saturates and its collector drops to
a low voltage, typically 50–100 mV. When A is LOW, the injection current is swept away from the
base-emitter junction of Q 1 . Transistor Q 1 becomes open and the injection current through Q 4 saturates
Q 2 , with the result that the Q 1 collector potential equals the base-emitter saturation voltage of Q 2 ,
typically 0.7 V.
The speed of I
2 L family devices is a function of the injection current I and improves with increase in
current, as a higher current allows a faster charging of capacitive loads present at bases of transistors.
The programmable injection current feature is made use of in the I
2 L family of digital ICs to choose
the desired speed depending upon intended application. The logic ‘0’ level is V CE (sat.) of the driving
transistor (Q 1 in the present case), and the logic ‘1’ level is V BE (sat.) of the driven transistor (Q 2
in the present case). Typically, the logic ‘0’ and logic ‘1’ levels are 0.1 and 0.7 V respectively. The
speed–power product of the I
2 L family is typically under 1 pJ.
Multiple collectors of different transistors can be connected together to form wired logic. Figure 5.60
shows one such arrangement, depicting the generation of OR and NOR outputs of two logic variables
A and B.