Logic Families
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5.7.1 PMOS Logic
The PMOS logic family uses P-channel MOSFETS. Figure 5.57(a) shows an inverter circuit using
PMOS logic. MOSFET Q 1 acts as an active load for the MOSFET switch Q 2 . For the circuit shown,
GND and −V DD respectively represent a logic ‘1’ and a logic ‘0’ for a positive logic system. When
the input is grounded (i.e. logic ‘1’), Q 2 remains in cut-off and −V DD appears at the output through
-V DD
A
Q 2
Q 1
Y = A
–V DD
Q 2
Q 3
Y = (A+B)
——
A
B
(a)
(b)
Q 1
Figure 5.57 (a) PMOS logic inverter and (b) PMOS logic two-input NOR.