148
Digital Electronics
5.4.1.2 MECL-10K Series
The MECL-10K family was introduced in 1971 to meet the requirements of more general-purpose highspeed applications. Another important feature of MECL-10K family devices is that they are compatible
with MECL-III devices, which facilitates the use of devices of the two families in the same system. The
increased propagation delay of 2 ns in the case of MECL-10K comes with the advantage of reduced
power dissipation, which is less than half the power dissipation in MECL-III family devices.
The basic characteristic parameters of MECL-10K are as follows: gate propagation delay = 2 ns
(10100-series) and 1.5 ns (10200-series); output edge speed = 3.5 ns (10100-series) and 2.5 ns (10200series); flip-flop toggle frequency = 125 MHz (min.) in the 10100-series and 200 MHz (min.) in the
10200-series; power dissipation per gate = 25 mW; speed–power product = 50 pJ (10100-series) and
37 pJ (10200-series); input voltage = 0–V EE (V EE is the negative supply voltage); negative power
supply range (for V CC = 0) = −4.68 to −5.72 V; continuous output source current (max.) = 50 mA;
surge output source current (max.) = 100 mA; operating temperature range = −30 °C to +85 °C.
5.4.1.3 MECL-10H Series
The MECL-10H family, introduced in 1981, combines the high speed advantage of MECL-III with
the lower power dissipation of MECL-10K. That is, it offers the speed of MECL-III with the power
economy of MECL-10K. Backed by a propagation delay of 1 ns and a power dissipation of 25 mW
per gate, MECL-10H offers one of the best speed–power product specifications in all available ECL
subfamilies. Another important aspect of this family is that many of the MECL-10H devices are pinout/functional replacements of MECL-10K series devices, which allows the users or the designers to
enhance the performance of existing systems by increasing speed in critical timing areas.
The basic characteristic parameters of MECL-10H are as follows: gate propagation delay = 1 ns;
output edge speed = 1 ns; flip-flop toggle frequency = 250 MHz (min.); power dissipation per
gate = 25 mW; speed–power product = 25 pJ; input voltage = 0–V EE (V EE is the negative supply
voltage); negative power supply range (for V CC = 0) = −4.94 to −5.46 V; continuous output source
current (max.) = 50 mA; surge output source current (max.) = 100 mA; operating temperature
range = 0 °C to + 75 °C.
5.4.1.4 MECL-10E Series (ECLinPS
TM and ECLinPSLite
TM )
The ECLinPS
TM family, introduced in 1987, has a propagation delay of the order of 0.5 ns.
ECLinPSLite
TM is a recent addition to the ECL family. It offers a propagation delay of the order of
0.2 ns. The ECLPro™ family of devices is a rapidly growing line of high-performance ECL logic,
offering a significant speed upgrade compared with the ECLinPSLite
TM devices.
5.4.2 Logic Gate Implementation in ECL
OR/NOR is the fundamental logic gate of the ECL family. Figure 5.32 shows a typical internal
schematic of an OR/NOR gate in the 10K-series MECL family. The circuit in essence comprises a
differential amplifier input circuit with one side of the differential pair having multiple transistors
depending upon the number of inputs to the gate, a voltage- and temperature-compensated bias network
and emitter follower outputs. The internal schematic of the 10H-series gate is similar, except that the
bias network is replaced with a voltage regulator circuit and the source resistor R EE of the differential
amplifier is replaced with a constant current source. Typical values of power supply voltages are
Digital Electronics
5.4.1.2 MECL-10K Series
The MECL-10K family was introduced in 1971 to meet the requirements of more general-purpose highspeed applications. Another important feature of MECL-10K family devices is that they are compatible
with MECL-III devices, which facilitates the use of devices of the two families in the same system. The
increased propagation delay of 2 ns in the case of MECL-10K comes with the advantage of reduced
power dissipation, which is less than half the power dissipation in MECL-III family devices.
The basic characteristic parameters of MECL-10K are as follows: gate propagation delay = 2 ns
(10100-series) and 1.5 ns (10200-series); output edge speed = 3.5 ns (10100-series) and 2.5 ns (10200series); flip-flop toggle frequency = 125 MHz (min.) in the 10100-series and 200 MHz (min.) in the
10200-series; power dissipation per gate = 25 mW; speed–power product = 50 pJ (10100-series) and
37 pJ (10200-series); input voltage = 0–V EE (V EE is the negative supply voltage); negative power
supply range (for V CC = 0) = −4.68 to −5.72 V; continuous output source current (max.) = 50 mA;
surge output source current (max.) = 100 mA; operating temperature range = −30 °C to +85 °C.
5.4.1.3 MECL-10H Series
The MECL-10H family, introduced in 1981, combines the high speed advantage of MECL-III with
the lower power dissipation of MECL-10K. That is, it offers the speed of MECL-III with the power
economy of MECL-10K. Backed by a propagation delay of 1 ns and a power dissipation of 25 mW
per gate, MECL-10H offers one of the best speed–power product specifications in all available ECL
subfamilies. Another important aspect of this family is that many of the MECL-10H devices are pinout/functional replacements of MECL-10K series devices, which allows the users or the designers to
enhance the performance of existing systems by increasing speed in critical timing areas.
The basic characteristic parameters of MECL-10H are as follows: gate propagation delay = 1 ns;
output edge speed = 1 ns; flip-flop toggle frequency = 250 MHz (min.); power dissipation per
gate = 25 mW; speed–power product = 25 pJ; input voltage = 0–V EE (V EE is the negative supply
voltage); negative power supply range (for V CC = 0) = −4.94 to −5.46 V; continuous output source
current (max.) = 50 mA; surge output source current (max.) = 100 mA; operating temperature
range = 0 °C to + 75 °C.
5.4.1.4 MECL-10E Series (ECLinPS
TM and ECLinPSLite
TM )
The ECLinPS
TM family, introduced in 1987, has a propagation delay of the order of 0.5 ns.
ECLinPSLite
TM is a recent addition to the ECL family. It offers a propagation delay of the order of
0.2 ns. The ECLPro™ family of devices is a rapidly growing line of high-performance ECL logic,
offering a significant speed upgrade compared with the ECLinPSLite
TM devices.
5.4.2 Logic Gate Implementation in ECL
OR/NOR is the fundamental logic gate of the ECL family. Figure 5.32 shows a typical internal
schematic of an OR/NOR gate in the 10K-series MECL family. The circuit in essence comprises a
differential amplifier input circuit with one side of the differential pair having multiple transistors
depending upon the number of inputs to the gate, a voltage- and temperature-compensated bias network
and emitter follower outputs. The internal schematic of the 10H-series gate is similar, except that the
bias network is replaced with a voltage regulator circuit and the source resistor R EE of the differential
amplifier is replaced with a constant current source. Typical values of power supply voltages are