142
Digital Electronics
Figure 5.24 Handling unused inputs of AND and NAND gates.
OR and NOR gates, which do not use a multi-emitter input transistor and use separate input transistors
instead, as shown in Fig. 5.28. In this case, the input loading is n times the loading of a single input
for both HIGH and LOW states.
5.3.11 Current Transients and Power Supply Decoupling
TTL family devices are prone to occurrence of narrow-width current spikes on the power supply line.
Current transients are produced when the totem-pole output stage of the device undergoes a transition
from a logic LOW to a logic HIGH state. The problem becomes severe when in a digital circuit a
large number of gates are likely to switch states at the same time. These current spikes produce voltage
spikes due to any stray inductance present on the line. On account of the large rate of change in current
in the current spike, even a small value of stray inductance produces voltage spikes large enough
adversely to affect the circuit performance.
Figure 5.29 illustrates the phenomenon. When the output changes from LOW to HIGH, there is
a small fraction of time when both the transistors are conducting because the pull-up transistor Q 3
has switched on and the pull-down transistor Q 4 has not yet come out of saturation. During this
small fraction of time, there is an increase in current drawn from the supply; I CCL experiences a
positive spike before it settles down to a usually lower I CCH . The presence of any stray capacitance
C across the output owing to any stray wiring capacitance or capacitance loading of the circuit being
fed also adds to the problem. The problem of voltage spikes on the power supply line is usually
overcome by connecting small-value, low-inductance, high-frequency capacitors between V CC terminal
and ground. It is standard practice to use a 0.01 or 0.1 F ceramic capacitor from V CC to ground. This
Digital Electronics
Figure 5.24 Handling unused inputs of AND and NAND gates.
OR and NOR gates, which do not use a multi-emitter input transistor and use separate input transistors
instead, as shown in Fig. 5.28. In this case, the input loading is n times the loading of a single input
for both HIGH and LOW states.
5.3.11 Current Transients and Power Supply Decoupling
TTL family devices are prone to occurrence of narrow-width current spikes on the power supply line.
Current transients are produced when the totem-pole output stage of the device undergoes a transition
from a logic LOW to a logic HIGH state. The problem becomes severe when in a digital circuit a
large number of gates are likely to switch states at the same time. These current spikes produce voltage
spikes due to any stray inductance present on the line. On account of the large rate of change in current
in the current spike, even a small value of stray inductance produces voltage spikes large enough
adversely to affect the circuit performance.
Figure 5.29 illustrates the phenomenon. When the output changes from LOW to HIGH, there is
a small fraction of time when both the transistors are conducting because the pull-up transistor Q 3
has switched on and the pull-down transistor Q 4 has not yet come out of saturation. During this
small fraction of time, there is an increase in current drawn from the supply; I CCL experiences a
positive spike before it settles down to a usually lower I CCH . The presence of any stray capacitance
C across the output owing to any stray wiring capacitance or capacitance loading of the circuit being
fed also adds to the problem. The problem of voltage spikes on the power supply line is usually
overcome by connecting small-value, low-inductance, high-frequency capacitors between V CC terminal
and ground. It is standard practice to use a 0.01 or 0.1 F ceramic capacitor from V CC to ground. This